A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories

An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond...

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Published in:IEEE transactions on circuits and systems. II, Express briefs Vol. 56; no. 11; pp. 865 - 869
Main Authors: Xueqiang, Wang, Liyang, Pan, Dong, Wu, Chaohong, Hu, Runde, Zhou
Format: Journal Article
Language:English
Published: New York IEEE 01.11.2009
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Chaos
Circuits
Decoders
Decoding
Delay
Error correction
Error correction codes
Error-correcting code (ECC)
fast-decoding algorithm
Flash memory
Flash memory (computers)
Galois fields
High speed
Iterative algorithms
Iterative decoding
Mathematical analysis
Microelectronics
multilevel-cell (MLC) nor flash memories
Transformations
two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder
ISSN:1549-7747, 1558-3791
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Abstract An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.
AbstractList An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in nor flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of nor flash memories.
Author Pan Liyang
Hu Chaohong
Wang Xueqiang
Wu Dong
Zhou Runde
Author_xml – sequence: 1
  givenname: Wang
  surname: Xueqiang
  fullname: Xueqiang, Wang
– sequence: 2
  givenname: Pan
  surname: Liyang
  fullname: Liyang, Pan
– sequence: 3
  givenname: Wu
  surname: Dong
  fullname: Dong, Wu
– sequence: 4
  givenname: Hu
  surname: Chaohong
  fullname: Chaohong, Hu
– sequence: 5
  givenname: Zhou
  surname: Runde
  fullname: Runde, Zhou
BookMark eNp9kc1OGzEUha2KSoSUF6Abq4uKzVD_jsdLOpAmUlCRCGvL47kDRpNxak-E-vb1kKgLFmyOLes7517rnKGTIQyA0AUlV5QS_WNTP6xWV4wQnYVpKsQnNKNSVgVXmp5Md6ELpYQ6RWcpvZAMEc5m6P4aL_3Tc_GwA2jx5jUUNfQ9_lkv8Q240ELEXYj4NsasdYgR3OiHJ-wHfLeu8ZBfF71Nz_gOtiF6SF_Q5872Cc6P5xw9Lm439bJY__61qq_XhRNMjIVzjFa8UZJxEA1RXDndkpKLlkBLiRRcNdrqxkrKSae7qqGu7aiWsqtaCyWfo--H3F0Mf_aQRrP1yeXd7QBhnwzPWaUWE3j5IUhLRVkpCJcZ_fYOfQn7OORvGE0ZV5WQUx47QC6GlCJ0Zhf91sa_hhIzlWHeyjBTGeZYRjZV70zOj3b0YRij9f3H1q8HqweA_7Mk05owxv8BKz-WGw
CODEN ICSPE5
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10.1109/TVLSI.2003.810782
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10.1109/82.633444
10.1109/76.212719
ContentType Journal Article
Copyright Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009
Copyright_xml – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009
DBID 97E
RIA
RIE
AAYXX
CITATION
7SP
8FD
L7M
F28
FR3
DOI 10.1109/TCSII.2009.2029144
DatabaseName IEEE Xplore (IEEE)
IEEE All-Society Periodicals Package (ASPP) 1998–Present
IEEE Electronic Library (IEL)
CrossRef
Electronics & Communications Abstracts
Technology Research Database
Advanced Technologies Database with Aerospace
ANTE: Abstracts in New Technology & Engineering
Engineering Research Database
DatabaseTitle CrossRef
Technology Research Database
Advanced Technologies Database with Aerospace
Electronics & Communications Abstracts
Engineering Research Database
ANTE: Abstracts in New Technology & Engineering
DatabaseTitleList
Engineering Research Database
Engineering Research Database
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore Digital Library
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
Discipline Engineering
EISSN 1558-3791
EndPage 869
ExternalDocumentID 2545537701
10_1109_TCSII_2009_2029144
5299022
Genre orig-research
GroupedDBID 0R~
29I
4.4
5VS
6IK
6J9
97E
AAJGR
AARMG
AASAJ
AAWTH
ABAZT
ABQJQ
ABVLG
ACIWK
AETIX
AGQYO
AGSQL
AHBIQ
AIBXA
AKJIK
AKQYR
ALMA_UNASSIGNED_HOLDINGS
ATWAV
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
EBS
EJD
IFIPE
IPLJI
JAVBF
M43
OCL
PZZ
RIA
RIE
RNS
RXW
TAE
TAF
VJK
AAYXX
CITATION
7SP
8FD
L7M
F28
FR3
ID FETCH-LOGICAL-c424t-cc2183b7523e4b0737c9d0634d0ed105437b9a9ba5130f9f8b1cdf1955f8dae63
IEDL.DBID RIE
ISICitedReferencesCount 15
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000271955800013&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN 1549-7747
IngestDate Sat Sep 27 19:48:15 EDT 2025
Sun Sep 28 09:26:50 EDT 2025
Sun Nov 30 05:30:36 EST 2025
Sat Nov 29 02:22:52 EST 2025
Tue Nov 18 19:50:36 EST 2025
Tue Aug 26 16:38:42 EDT 2025
IsPeerReviewed true
IsScholarly true
Issue 11
Language English
License https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-c424t-cc2183b7523e4b0737c9d0634d0ed105437b9a9ba5130f9f8b1cdf1955f8dae63
Notes ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ObjectType-Article-1
ObjectType-Feature-2
content type line 23
PQID 912378456
PQPubID 23500
PageCount 5
ParticipantIDs crossref_citationtrail_10_1109_TCSII_2009_2029144
proquest_miscellaneous_1671264035
crossref_primary_10_1109_TCSII_2009_2029144
proquest_miscellaneous_36346946
proquest_journals_912378456
ieee_primary_5299022
PublicationCentury 2000
PublicationDate 2009-11-01
PublicationDateYYYYMMDD 2009-11-01
PublicationDate_xml – month: 11
  year: 2009
  text: 2009-11-01
  day: 01
PublicationDecade 2000
PublicationPlace New York
PublicationPlace_xml – name: New York
PublicationTitle IEEE transactions on circuits and systems. II, Express briefs
PublicationTitleAbbrev TCSII
PublicationYear 2009
Publisher IEEE
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml – name: IEEE
– name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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SSID ssj0029032
Score 1.9654452
Snippet An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To...
SourceID proquest
crossref
ieee
SourceType Aggregation Database
Enrichment Source
Index Database
Publisher
StartPage 865
SubjectTerms Chaos
Circuits
Decoders
Decoding
Delay
Error correction
Error correction codes
Error-correcting code (ECC)
fast-decoding algorithm
Flash memory
Flash memory (computers)
Galois fields
High speed
Iterative algorithms
Iterative decoding
Mathematical analysis
Microelectronics
multilevel-cell (MLC) nor flash memories
Transformations
two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder
Title A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories
URI https://ieeexplore.ieee.org/document/5299022
https://www.proquest.com/docview/912378456
https://www.proquest.com/docview/1671264035
https://www.proquest.com/docview/36346946
Volume 56
WOSCitedRecordID wos000271955800013&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
journalDatabaseRights – providerCode: PRVIEE
  databaseName: IEEE Xplore Digital Library
  customDbUrl:
  eissn: 1558-3791
  dateEnd: 99991231
  omitProxy: false
  ssIdentifier: ssj0029032
  issn: 1549-7747
  databaseCode: RIE
  dateStart: 20040101
  isFulltext: true
  titleUrlDefault: https://ieeexplore.ieee.org/
  providerName: IEEE
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8NAEB60eNCDbzE-V_Cmq0mzyWaPGlsUVAQreAvZR7BQUklb_fvObtOg-AAvISS7JMxkd74v8wI49jXjeR6EVBRtThnzJbXpmdRPhI6YYUhJlGs2we_vk-dn8TAHp00ujDHGBZ-ZM3vqfPl6qCb2V9l5ZPfONm6485zH01ythlwJ3zUjsxXHEDEyPkuQ8cV5L328uZmWpkSqL5BCfDFCrqvKt63Y2Zfuyv_ebBWWaxxJLqaKX4M5U67D0qfqghvwcEFsFAd9fEULRXrvQ5qawYBcptfkythU9oogYiWdqsJjart0KBsDTfolubtNSYlXu4itX8idjcZFRr0JT91OL72mdQMFqlibjalSFgBJjmTTMImLmSuhEZMw7RuNwIqFXIpcyDxCS1aIIpGB0kUgoqhIdG7icAta5bA020CQJZkEpyEikyySOuFKxjzEKXlY5KrtQTCTaKbq6uK2ycUgcyzDF5nTgu16KbJaCx6cNHNep7U1_hy9YeXejKxF7sHuTHFZvfxGmUB7zBPEhh4cNXdx3VhnSF6a4WSUBTEPEAz6YeTB4S9jQhRVLFi88_Ojd2HR-ZZcZuIetMbVxOzDgnob90fVgfs8PwC9bd8M
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3fa9swED5CV-j2sP7Ixrx2rQp9a7XasWxZj63bkNAkFJJC3oz1w7QQnOIk27-_k-KYlbaDvRhjS9joLN33WXf3AZz5mvE8D0Iqig6njPmS2vRM6idCR8wwpCTKiU3w0SiZTsV9Cy6aXBhjjAs-Mz_tqdvL13O1sr_KLiO7dnZwwf1glbPqbK2GXgnfyZHZmmOIGRnfpMj44nKSjvv9dXFKJPsCScQLN-R0VV4txs7DdHf_79324HONJMnV2vT70DLlAXz6q75gG-6viI3joONn9FFk8ntOUzObkeu0R26MTWavCGJWcltVeEytToeyUdDkqSTDQUpKvNpFdP1IhjYeFzn1F3jo3k7SHq0lFKhiHbakSlkIJDnSTcMkTmeuhEZUwrRvNEIrFnIpciHzCH1ZIYpEBkoXgYiiItG5icOvsFXOS_MNCPIkk2A3xGSSRVInXMmYh9glD4tcdTwINiOaqbq-uJW5mGWOZ_gic1awupciq63gwXnT53ldXeOfrdt23JuW9ZB7cLgxXFZPwEUm0CPzBNGhB6fNXZw5djskL818tciCmAcIB_0w8uDknTYhDlUsWPz97UefwE5vMhxkg_7o7hA-up0ml6d4BFvLamV-wLb6tXxaVMfuU_0DhJ_iVQ
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+High-Speed+Two-Cell+BCH+Decoder+for+Error+Correcting+in+MLC+nor+Flash+Memories&rft.jtitle=IEEE+transactions+on+circuits+and+systems.+II%2C+Express+briefs&rft.au=Xueqiang%2C+Wang&rft.au=Liyang%2C+Pan&rft.au=Dong%2C+Wu&rft.au=Chaohong%2C+Hu&rft.date=2009-11-01&rft.issn=1549-7747&rft.volume=56&rft.issue=11&rft.spage=865&rft.epage=869&rft_id=info:doi/10.1109%2FTCSII.2009.2029144&rft.externalDBID=NO_FULL_TEXT
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1549-7747&client=summon
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1549-7747&client=summon
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1549-7747&client=summon