Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder

Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. T...

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Vydáno v:IEEE transactions on circuits and systems. I, Regular papers Ročník 54; číslo 5; s. 1060 - 1068
Hlavní autoři: Sun, F, Zhang, T
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.05.2007
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Adaptive algorithms
Adaptive Viterbi algorithm
Algorithm design and analysis
Algorithms
Circuits
Computational complexity
Convolutional codes
Decoders
Decoding
Delay
low power
Searching
Silicon
Sun
T -algorithm
Throughput
Very large scale integration
very large-scale integration (VLSI) architecture
Viterbi algorithm
Viterbi decoders
ISSN:1549-8328, 1558-0806
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Shrnutí:Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. This limitation also incurs power and silicon area overhead. This paper presents a modified adaptive Viterbi algorithm, referred to as the relaxed adaptive Viterbi algorithm, that completely eliminates the global best survivor path metric search operation. A state-parallel decoder VLSI architecture has been developed to implement the relaxed adaptive Viterbi algorithm. Using convolutional code decoding as a test vehicle, we demonstrate that state-parallel relaxed adaptive Viterbi decoders, versus Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and very high throughput
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ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2007.890617