Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design

Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constr...

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Published in:	IEEE transactions on circuits and systems. I, Regular papers Vol. 55; no. 2; pp. 572 - 585
Main Authors:	Zhang, Haibin, Zhu, Jia, Shi, Huifeng, Wang, Dawei
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2008 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Algorithms Architecture Code construction Coders Complexity Costs decoder Decoders encoder Encoders Encoding Hardware hardware architecture Iterative algorithms Iterative decoding low-density parity check (LDPC) Matrices Networks Parallel architectures Parity check codes Research and development Sparse matrices Throughput Low-density parity-check (LDPC) code construction decoder hardware architecture encoder
ISSN:	1549-8328, 1558-0806
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Abstract	Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate.
AbstractList	Layered approximately regular (LAR) low-density parity-check (LDPC) codes are proposed, with which one single pair of encoder and decoder support various code lengths and code rates. The parity check matrices of LAR-LDPC codes have a "layer-block-cell" structure with some additional constraints. An encoder architecture is then designed for LAR-LDPC codes, by making two improvements to the Richardson-Urbanke approach: the forward substitution operation is entirely removed and the dense-matrix-vector multiplication is handled using feedback shift-registers. A partially parallel decoder architecture is also designed for LAR-LDPC codes, where a layered modified min-sum decoding algorithm is used to trade off among complexity, speed, and performance. More importantly, the interconnection network, which is inevitable for partially parallel decoders, has much lower hardware complexity compared with that for general LDPC codes. Both the encoder and decoder architectures are highly flexible in code length and code rate.
Author	Wang, Dawei Zhu, Jia Shi, Huifeng Zhang, Haibin
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SubjectTerms	Algorithms Architecture Code construction Coders Complexity Costs decoder Decoders encoder Encoders Encoding Hardware hardware architecture Iterative algorithms Iterative decoding low-density parity check (LDPC) Matrices Networks Parallel architectures Parity check codes Research and development Sparse matrices Throughput
Title	Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design
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