A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing

High-density SRAMs utilize aggressively small bit-cells, which are subject to extreme variability, degrading their read SNM and read-current. Additionally, array performance is also limited by sense-amplifier offset and strobe-timing uncertainty. This paper, presents a sense-amplifier that targets a...

Celý popis

Uložené v:

Podrobná bibliografia
Vydané v:	IEEE journal of solid-state circuits Ročník 44; číslo 1; s. 163 - 173
Hlavní autori:	Verma, N., Chandrakasan, A.P.
Médium:	Journal Article Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	New York, NY IEEE 01.01.2009 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Access time Applied sciences Arrays Auto-zeroing CMOS technology Compensation Degradation Design. Technologies. Operation analysis. Testing Detection device variation Electric potential Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Energy consumption Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Manufacturing offset compensation Offsets Performance degradation Prototypes Random access memory Regenerative Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices sense-amplifier SRAM Target tracking Topology Uncertainty Voltage Performance evaluation offset compensation Static random access memory Access time Prototype High density Small signal behavior Random access memory Auto-zeroing sense-amplifier Regenerative process Mismatching SRAM Optimization Sense amplifier Trigger Voltage standard device variation Complementary MOS technology Integrated circuit Low-power electronics Signal detection Damaging
ISSN:	0018-9200, 1558-173X
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!

Popis
Shrnutí:	High-density SRAMs utilize aggressively small bit-cells, which are subject to extreme variability, degrading their read SNM and read-current. Additionally, array performance is also limited by sense-amplifier offset and strobe-timing uncertainty. This paper, presents a sense-amplifier that targets all of these performance degradations: specifically, simple offset compensation reduces sensitivity to variation while imposing minimal loading on high-speed nodes; stable internal voltage references serve as an internal means to self-trigger regeneration to avoid tracking mismatch in an external strobe-path; precise small-signal detection withstands small read-currents so that other bit-cell parameters can be optimized; and single-ended sensing provides compatibility to asymmetric bit-cells, which can have improved operating margins. The design is integrated with a 64-kb high-density array composed of 0.25 mum 2 6T bit-cells. A prototype, in low-power 45 nm CMOS, compares its performance with a conventional sense-amplifier, demonstrating an improvement of 4X in access-time sigma and 34% in overall worst case access time.
Bibliografia:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23
ISSN:	0018-9200 1558-173X
DOI:	10.1109/JSSC.2008.2006428