An Efficient and Scalable Semiconductor Architecture for Parallel Automata Processing

We present the design and development of the automata processor, a massively parallel non-von Neumann semiconductor architecture that is purpose-built for automata processing. This architecture can directly implement non-deterministic finite automata in hardware and can be used to implement complex...

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Veröffentlicht in:IEEE transactions on parallel and distributed systems Jg. 25; H. 12; S. 3088 - 3098
Hauptverfasser: Dlugosch, Paul, Brown, Dave, Glendenning, Paul, Leventhal, Michael, Noyes, Harold
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
accelerator architectures
Architecture (computers)
Arrays
Automata
Biology
Complexity theory
Computer information security
Hardware
high performance computing
Mathematical analysis
Microprocessors
parallel architectures
Radiation detectors
reconfigurable architectures
Routing
Semiconductors
Transaction processing
ISSN:1045-9219, 1558-2183
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Zusammenfassung:We present the design and development of the automata processor, a massively parallel non-von Neumann semiconductor architecture that is purpose-built for automata processing. This architecture can directly implement non-deterministic finite automata in hardware and can be used to implement complex regular expressions, as well as other types of automata which cannot be expressed as regular expressions. We demonstrate that this architecture exceeds the capabilities of high-performance FPGA-based implementations of regular expression processors. We report on the development of an XML-based language for describing automata for easy compilation targeted to the hardware. The automata processor can be effectively utilized in a diverse array of applications driven by pattern matching, such as cyber security and computational biology.
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ISSN:1045-9219
1558-2183
DOI:10.1109/TPDS.2014.8