Binarized Neural Network Comprising Quasi‐Nonvolatile Memory Devices for Neuromorphic Computing

This study presents a binarized neural network (BNN) comprising quasi‐nonvolatile memory (QNVM) devices that operate in a positive feedback loop mechanism and exhibit an extremely low subthreshold swing (≤ 5 mV dec−1) and a high on/off ratio (≥ 107). A pair of QNVM devices are used for a single syna...

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Vydané v:Advanced electronic materials Ročník 10; číslo 9
Hlavní autori: Shin, Yunwoo, Jeon, Juhee, Cho, Kyoungah, Kim, Sangsig
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Seoul John Wiley & Sons, Inc 01.09.2024
Wiley-VCH
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ISSN:2199-160X, 2199-160X
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Shrnutí:This study presents a binarized neural network (BNN) comprising quasi‐nonvolatile memory (QNVM) devices that operate in a positive feedback loop mechanism and exhibit an extremely low subthreshold swing (≤ 5 mV dec−1) and a high on/off ratio (≥ 107). A pair of QNVM devices are used for a single synaptic cell in a cell array, in which its memory state represents the synaptic weight, and the voltages applied to the pair act as input in a complementary fashion. The array of synaptic cells performs matrix multiply‐accumulate (MAC) operations between the weight matrix and input vector using XNOR and current summation. All the results of the MAC operations and vector‐matrix multiplications are equivalent. Moreover, the BNN features a high accuracy of 93.32% in the MNIST image recognition simulation owing to high device uniformity (1.35%), which demonstrates the feasibility of compact and high‐performance neuromorphic computing. In this study, quasi‐nonvolatile memory devices with the p+‐n‐p‐n+ structure are proposed as synaptic devices. The 2×2 synaptic cell array demonstrates the matrix multiply‐accumulate operations using XNOR and current summations. Furthermore, binarized neural network achieves high accuracy (93.32%) in MNIST image recognition simulation. Consequently, the devices provide synaptic cell array for high‐performance compact neuromorphic computing architecture.
Bibliografia:ObjectType-Article-1
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content type line 14
ISSN:2199-160X
2199-160X
DOI:10.1002/aelm.202400061