Accelerating floating-point to fixed-point data type conversion with evolutionary algorithms
The choice of the data type representation has significant impacts on the resource utilisation, maximum clock frequency and power consumption of any hardware design. Although arithmetic hardware units for the fixed-point format can improve performance and reduce energy consumption, the process of tu...
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| Published in: | Electronics letters Vol. 51; no. 3; pp. 244 - 246 |
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| Main Authors: | , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
The Institution of Engineering and Technology
05.02.2015
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| Subjects: | |
| ISSN: | 0013-5194, 1350-911X, 1350-911X |
| Online Access: | Get full text |
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| Summary: | The choice of the data type representation has significant impacts on the resource utilisation, maximum clock frequency and power consumption of any hardware design. Although arithmetic hardware units for the fixed-point format can improve performance and reduce energy consumption, the process of tuning the right bit length is known as a time-consuming task, since it is a combinatorial optimisation problem guided by the accumulative arithmetic computation error. A novel evolutionary approach to accelerate the process of converting algorithms from the floating-point to fixed-point format is presented. Results are demonstrated by converting three computing-intensive algorithms from the mobile robotic scenario, where data error accumulated during execution is influenced by external factors, such as sensor noise and navigation environment characteristics. The proposed evolutionary algorithm accelerated the conversion process by up to 2.5 × against the state-of-the-art methods, allowing even further bit-length optimisations. |
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| Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
| ISSN: | 0013-5194 1350-911X 1350-911X |
| DOI: | 10.1049/el.2014.3791 |