A high performance ST-Box based unified AES encryption/decryption architecture on FPGA

•A single integrated and symmetric ST-Box structure followed by a single XOR Network is proposed for a unified AES encryptor and decryptor architecture.•Switching capabilities of BRAM are explored to maximize the performance of system by proposing a duty-cycle based accessing technique.•The Effectiv...

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Bibliographic Details
Published in:	Microprocessors and microsystems Vol. 41; pp. 37 - 46
Main Authors:	Kundi, D.-S., Aziz, Arshad, Ikram, Nassar
Format:	Journal Article
Language:	English
Published:	Elsevier B.V 01.03.2016
Subjects:	AES Architecture Asymmetry Blocking BRAM Clocks Encryption Field programmable gate arrays FPGA Hardware Look-Up-Table Symmetry Unified encryptor and decryptor Unified encryptor and decryptor BRAM FPGA AES Look-Up-Table
ISSN:	0141-9331, 1872-9436
Online Access:	Get full text
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