Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry - Quintarelli, Giovanni; Bertolucci, Matteo; Nannipieri, Pietro (IEEE access, 2023)
To ensure the flexibility of Earth Observation satellite missions, it is essential to have highly adaptable communication systems equipped with efficient modulation and coding schemes. The preferred approach for such applications is the DVB-S2 standard, which provides three operational modes: Constant Coding and Modulation, Variable Coding and Modulation, and Adaptive Coding and Modulation. Additionally, this standard incorporates a robust Forward Error Correction system that combines a Low-Density Parity-Check encoder with a Bose-Chaudhuri-Hocquenghem encoder. This combination ensures optimal utilization of channel bandwidth while maintaining an acceptable Bit Error Rate throughout the satellite's orbit. This research is centred on designing and implementing a highly flexible and high-speed parallel Bose-Chaudhuri-Hocquenghem encoder, fully compliant with the DVB-S2 standard, and supporting all Constant Coding and Modulation, Variable Coding and Modulation, and Adaptive Coding and Modulation modes. In contrast to existing solutions, our proposed encoder permits the concurrent processing of a larger number of bits, thereby enhancing parallelism. Furthermore, parallelism is a configurable parameter, allowing seamless system scalability. The proposed encoder can be tailored to accommodate a wide range of throughput requirements, making it suitable for various mission classes. This flexibility enables users to balance factors like complexity, power consumption, and performance. The hardware platform selected for circuit implementation is the space-grade Xilinx XQRKU060 FPGA. Our results demonstrate a maximum achievable throughput ranging from 600 Mbps to 19.2 Gbps and a dynamic power consumption of 10 mW to 79 mW, depending on the chosen parallelism level (ranging from 2 to 96). The optimization of resource utilization is particularly noteworthy, as it reduces the required resources to as low as 760 Look-up Tables and 344 registers for lower parallelism levels.