Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

To address the challenges posed by propagation channel impairments and to meet the high data rate requirements of laser communications, this study introduces a pioneering low-density parity-check (LDPC) decoder characterized by its high throughput and low complexity. The unique design of this decode...

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Bibliographic Details
Published in:IEEE access Vol. 12; pp. 33328 - 33336
Main Authors: Kang, Jing, An, Junshe, Zhu, Yan
Format: Journal Article
Language:English
Published: Piscataway IEEE 2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Complexity
Computer architecture
Decoders
Decoding
Error correcting codes
Field programmable gate arrays
FPGA
Hardware
high-throughput
Iterative decoding
laser communications
Lasers
LDPC decoder
low-complexity
Message passing
Optical communication
Parity check codes
Pipelining (computers)
Random access memory
Throughput
ISSN:2169-3536, 2169-3536
Online Access:Get full text
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Summary:To address the challenges posed by propagation channel impairments and to meet the high data rate requirements of laser communications, this study introduces a pioneering low-density parity-check (LDPC) decoder characterized by its high throughput and low complexity. The unique design of this decoder, based on an inter-frame pipeline and intra-frame parallel (IFPP-IFP) scheme, is specifically tailored to maximize the efficiency of processing units, leading to a substantial increase in decoding throughput. The implementation of IFPP is realized through a novel full-overlap message passing (FOMP) scheme and a dynamic address access (DAA) algorithm, distinguishing it from current solutions. Additionally, the decoder employs a message packing strategy and low-complexity data alignment units to effectively achieve IFP. Compared to existing solutions, our hardware implementation on the Xilinx XCKU060 FPGA demonstrates significant progress. The decoder achieves a decoding throughput of 2.67 Gb/s at 10 iterations and 350MHz. Remarkably, when five decoders are used on a single FPGA device, the throughput soars to 13.3 Gb/s, outperforming state-of-the-art designs by 1.3 times and concurrently reducing resource consumption by half. This combination of resource efficiency and enhanced throughput highlights the innovative and superior nature of our proposed approach.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2024.3371188