A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon Decomposition

In this paper, we describe a new verification method to accelerate the input negation and/or input permutation and/or output negation (NPN) Boolean matching for a single-output completely specified Boolean function. Through research on the Boolean Shannon decomposition binary tree, we prove that the...

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Vydáno v:IEEE access Ročník 10; s. 120369 - 120382
Hlavní autoři: Zhang, Juling, Guo, Wenqiang, Yang, Guowu, Zhu, Yixin, Lv, Xiaoyi
Médium: Journal Article
Jazyk:angličtina
Vydáno: Piscataway IEEE 2022
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Algorithms
Benchmarks
Binary trees
Boolean
Boolean functions
Boolean matching
Circuits
Cyberspace
Decomposition
Finance
Impedance matching
Independent variables
Information theory
Iterative methods
Matching
Nodes
NPN equivalence
Permutations
Runtime
Shannon decomposition binary tree
Shannon expansion
signature vector
Transformations (mathematics)
Verification
ISSN:2169-3536, 2169-3536
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Shrnutí:In this paper, we describe a new verification method to accelerate the input negation and/or input permutation and/or output negation (NPN) Boolean matching for a single-output completely specified Boolean function. Through research on the Boolean Shannon decomposition binary tree, we prove that the signature vectors of the left child node and right child node are complementary relative to the signature vector of the parent node. We introduce an independent variable check to speed up the detection of candidate transformation. The proposed approach utilises this complementarity, a symmetry check, an independent variable check and a phase collision check, which can quickly verify whether the candidate transformation obtained in the detection of the candidate transformation of the Boolean matching process is accurate. We perform experiments on two types of Boolean function sets. One type consists of Boolean functions from randomly generated circuits. The other is exported from the Microelectronics Center of North Carolina (MCNC) benchmark. The experimental results show that the average runtime of our algorithm is 68.8% faster than those in Zhang et al. (2019) on two randomly generated circuits and 51% faster than those in Zhang et al. (2019) when tested on the MCNC benchmark circuit set. Therefore, the experimental results demonstrate the effectiveness of the proposed method.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2022.3221764