Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodolog...

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Bibliographic Details
Published in:IEEE access Vol. 7; pp. 40674 - 40694
Main Authors: Coutinho, Maria G. F., Torquato, Matheus F., Fernandes, Marcelo A. C.
Format: Journal Article
Language:English
Published: Piscataway IEEE 2019
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Algorithms
Artificial neural networks
Computer architecture
Deep learning
Field programmable gate arrays
FPGA
Graphics processing units
Hardware
Machine learning
Neural networks
Reconfigurable hardware
stacked sparse autoencoder
systolic array
Throughput
ISSN:2169-3536, 2169-3536
Online Access:Get full text
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Summary:Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodologies focusing on accelerating complex algorithms including those based on reconfigurable hardware has been showing significant results. Therefore, the objective of this paper is to propose a neural network hardware implementation to be used in deep learning applications. The implementation was developed on a field-programmable gate array (FPGA) and supports deep neural network (DNN) trained with the stacked sparse autoencoder (SSAE) technique. In order to allow DNNs with several inputs and layers on the FPGA, the systolic array technique was used in the entire architecture. Details regarding the designed implementation were evidenced, as well as the hardware area occupation and the processing time for two different implementations. The results showed that both implementations achieved high throughput enabling deep learning techniques to be applied for problems with large data amounts.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2019.2907261