Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodolog...

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Veröffentlicht in:	IEEE access Jg. 7; S. 40674 - 40694
Hauptverfasser:	Coutinho, Maria G. F., Torquato, Matheus F., Fernandes, Marcelo A. C.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Piscataway IEEE 2019 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithms Artificial neural networks Computer architecture Deep learning Field programmable gate arrays FPGA Graphics processing units Hardware Machine learning Neural networks Reconfigurable hardware stacked sparse autoencoder systolic array Throughput
ISSN:	2169-3536, 2169-3536
Online-Zugang:	Volltext
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