A High-Throughput FPGA Architecture for Joint Source and Channel Decoding

In the wireless transmission of multimedia information, the achievable transmission throughput and latency may be limited by the processing throughput and latency associated with source and channel coding. Ultra-high throughput and ultra-low latency processing of source and channel coding are requir...

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Vydáno v:IEEE access Ročník 5; s. 2921 - 2944
Hlavní autoři: Brejza, Matthew F., Maunder, Robert G., Al-Hashimi, Bashir M., Hanzo, Lajos
Médium: Journal Article
Jazyk:angličtina
Vydáno: Piscataway IEEE 2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
channel coding
channel coding, decoding
Coding
combined source-channel coding
Decoding
Error correction
Field programmable gate arrays
Hardware
Iterative decoding
Long Term Evolution
Multimedia
Network latency
Remote control
Throughput
Turbo codes
Unmanned vehicles
Video transmission
wireless communication
ISSN:2169-3536, 2169-3536
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Shrnutí:In the wireless transmission of multimedia information, the achievable transmission throughput and latency may be limited by the processing throughput and latency associated with source and channel coding. Ultra-high throughput and ultra-low latency processing of source and channel coding are required by the emerging new video transmission applications, such as the first-person remote control of unmanned vehicles. The recently proposed unary error correction (UEC) code facilitates the joint source and channel coding (JSCC) of video information at transmission throughputs that approach the capacity of the wireless channel. In this paper, we propose the first hardware implementation of the UEC code that achieves the high processing throughputs as well as ultra-low processing latencies required. This is achieved by extending the application of the recently proposed fully parallel turbo decoder (FPTD) from pure stand-alone channel coding to JSCC. This paper also proposes several novel improvements to the FPTD, in order to increase its hardware efficiency and supported frame length. We demonstrate the application of these improvements to both the long term evolution turbo code and the UEC code. We synthesize the proposed fully parallel design on a mid-range field programmable gate array, achieving a throughput of 450 Mbps, as well as a factor of 2.4 hardware efficiency improvement over previous implementations of the FPTD.
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ISSN:2169-3536
2169-3536
DOI:10.1109/ACCESS.2016.2633441