True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance

This brief presents a technique that can fully exploit the data dependency of flash memory cell damage to improve the program/erase (P/E) cycling endurance of nand flash memory. The key is to opportunistically leverage data lossless compressibility and utilize the compression gain to realize memory-...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 6; pp. 1165 - 1169
Main Authors: Li, Jiangpeng, Zhao, Kai, Ma, Jun, Zhang, Tong
Format: Journal Article
Language:English
Published: IEEE 01.06.2015
Subjects:
Ash
Bit error rate
Data compression
Encoding
Endurance
enumerative coding
Memory management
Microprocessors
NAND flash memory
Endurance
enumerative coding
nand flash memory
ISSN:1063-8210, 1557-9999
Online Access:Get full text
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Summary:This brief presents a technique that can fully exploit the data dependency of flash memory cell damage to improve the program/erase (P/E) cycling endurance of nand flash memory. The key is to opportunistically leverage data lossless compressibility and utilize the compression gain to realize memory-damage-aware data manipulation to reduce the cycling-induced physical damage. Based upon experiments using commercial sub-22-nm MLC nand flash memory chips, we show that the proposed design technique can improve the P/E cycling endurance by 50%. We further carried out application-specific integrated circuit design to demonstrate the practical feasibility for implementing the proposed design technique.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2014.2332099