Communication-hiding programming for clusters with multi-coprocessor nodes
Summary Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new off...
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| Vydané v: | Concurrency and computation Ročník 27; číslo 16; s. 4172 - 4185 |
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| Hlavní autori: | , , , , , |
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| Jazyk: | English |
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Blackwell Publishing Ltd
01.11.2015
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| Abstract | Summary
Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new offload approach is considered for intra‐node communication, which combines Intel's APIs of coprocessor offload infrastructure (COI) and symmetric communication interface (SCIF) for achieving low latency. While the conventional pragma‐based offload approach allows simpler programming, the COI‐SCIF approach has three advantages in (1) lower overhead associated with launching offloaded code, (2) higher data transfer bandwidths, and (3) more advanced asynchrony between computation and data movement. The low‐level COI‐SCIF approach is also shown to have benefits over the MPI‐OpenMP counterpart, which belongs to the symmetric usage mode. Moreover, a hybird programming strategy based on COI‐SCIF is presented for joining the computational force of all CPUs and coprocessors, while realizing communication hiding. All the programming approaches are tested by a real‐world 3D application, for which the COI‐SCIF‐based approach shows a performance advantage on Tianhe‐2. Copyright © 2015 John Wiley & Sons, Ltd. |
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| AbstractList | Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new offload approach is considered for intra‐node communication, which combines Intel's APIs of
coprocessor offload infrastructure
(COI) and
symmetric communication interface
(SCIF) for achieving low latency. While the conventional pragma‐based offload approach allows simpler programming, the COI‐SCIF approach has three advantages in (1) lower overhead associated with launching offloaded code, (2) higher data transfer bandwidths, and (3) more advanced asynchrony between computation and data movement. The low‐level COI‐SCIF approach is also shown to have benefits over the MPI‐OpenMP counterpart, which belongs to the symmetric usage mode. Moreover, a hybird programming strategy based on COI‐SCIF is presented for joining the computational force of all CPUs and coprocessors, while realizing communication hiding. All the programming approaches are tested by a real‐world 3D application, for which the COI‐SCIF‐based approach shows a performance advantage on Tianhe‐2. Copyright © 2015 John Wiley & Sons, Ltd. Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new offload approach is considered for intra-node communication, which combines Intel's APIs of coprocessor offload infrastructure (COI) and symmetric communication interface (SCIF) for achieving low latency. While the conventional pragma-based offload approach allows simpler programming, the COI-SCIF approach has three advantages in (1) lower overhead associated with launching offloaded code, (2) higher data transfer bandwidths, and (3) more advanced asynchrony between computation and data movement. The low-level COI-SCIF approach is also shown to have benefits over the MPI-OpenMP counterpart, which belongs to the symmetric usage mode. Moreover, a hybird programming strategy based on COI-SCIF is presented for joining the computational force of all CPUs and coprocessors, while realizing communication hiding. All the programming approaches are tested by a real-world 3D application, for which the COI-SCIF-based approach shows a performance advantage on Tianhe-2. Summary Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this paper investigates the particular topic of programming clusters that have multiple Xeon Phi coprocessors in each compute node. A new offload approach is considered for intra‐node communication, which combines Intel's APIs of coprocessor offload infrastructure (COI) and symmetric communication interface (SCIF) for achieving low latency. While the conventional pragma‐based offload approach allows simpler programming, the COI‐SCIF approach has three advantages in (1) lower overhead associated with launching offloaded code, (2) higher data transfer bandwidths, and (3) more advanced asynchrony between computation and data movement. The low‐level COI‐SCIF approach is also shown to have benefits over the MPI‐OpenMP counterpart, which belongs to the symmetric usage mode. Moreover, a hybird programming strategy based on COI‐SCIF is presented for joining the computational force of all CPUs and coprocessors, while realizing communication hiding. All the programming approaches are tested by a real‐world 3D application, for which the COI‐SCIF‐based approach shows a performance advantage on Tianhe‐2. Copyright © 2015 John Wiley & Sons, Ltd. |
| Author | Zhao, Mandan Wen, Mei Cai, Xing Chai, Jun Zhang, Chunyuan Dong, Xinnan |
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| Cites_doi | 10.1177/1094342013514465 10.1016/j.procs.2013.05.430 10.1145/2503210.2503288 10.1145/2493123.2462921 10.1109/IPDPSW.2013.179 10.1109/IPDPS.2013.113 10.1145/2484762.2484779 10.1109/HOTCHIPS.2012.7476487 10.1109/IPDPS.2013.44 |
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| References_xml | – reference: Chai J, Hake J, Wu N, Wen M, Cai X, Lines GT, Yang J, Su H, Zhang C, Liao X. Towards simulation of subcellular calcium dynamics at nanometre resolution. International Journal of High Performance Computing Applications 2013; 29(1):51-63. – reference: Rosales C. Porting to the Intel Xeon Phi: Opportunities and Challenges, Extreme Scaling Workshop (XSCALE13). IEEE: Colorado, U.S.A, 2013. – reference: Chen C, Yang C, Tang T, Wu Q, Zhang P. OpenACC to Intel Offload: Automatic Translation and Optimization, Computer Engineering and Technology. Springer: Heidelberg 2013; 111-120. – reference: Jeffers J, Reinders J. Intel Xeon Phi Coprocessor High-Performance Programming. Morgan Kaufmann: Amsterdam, 2013. – year: 2014 article-title: Intel Manycore Platform Software Stack (MPSS) – year: 2012 article-title: MIC SCIF API reference manual 0.65 for user mode Linux – start-page: 1 year: 2012 end-page: 6 – year: 2013 article-title: Visit to the National University for Defense Technology Changsha, China – year: 2012 article-title: Intel Xeon Phi coprocessor – the architecture – year: 2013 article-title: OFS for Xeon Phi – start-page: 126 year: 2013 end-page: 137 – volume: 29 start-page: 51 issue: 1 year: 2013 end-page: 63 article-title: Towards simulation of subcellular calcium dynamics at nanometre resolution publication-title: International Journal of High Performance Computing Applications – year: 2013 article-title: The heterogeneous offload model for Intel many integrated core architecture – start-page: 48:1 year: 2013 end-page: 48:8 – year: 2014 article-title: Intel Xeon Phi Coprocessor System Software Developers Guide – start-page: 215 year: 2013 end-page: 226 – start-page: 1 year: 2013 end-page: 11 – start-page: 2508 year: 2013 end-page: 2511 – start-page: 1085 year: 2013 end-page: 1097 – year: 2012 article-title: MIC COI API reference manual 0.65 – year: 1992 article-title: MPICH: High‐performance and portable MPI – year: 2013 article-title: China's Tianhe‐2 Supercomputer takes No.1 ranking on 41st TOP500 list – start-page: 816 year: 2013 end-page: 824 – year: 2012 article-title: Intel Xeon Phi Coprocessor Instruction Set Architecture Reference manual – start-page: 111 year: 2013 end-page: 120 – year: 2013 – ident: e_1_2_8_2_1 – ident: e_1_2_8_10_1 – ident: e_1_2_8_25_1 doi: 10.1177/1094342013514465 – ident: e_1_2_8_19_1 doi: 10.1016/j.procs.2013.05.430 – ident: e_1_2_8_16_1 – ident: e_1_2_8_20_1 – ident: e_1_2_8_13_1 doi: 10.1145/2503210.2503288 – ident: e_1_2_8_11_1 – ident: e_1_2_8_17_1 – ident: e_1_2_8_3_1 – ident: e_1_2_8_8_1 – ident: e_1_2_8_18_1 doi: 10.1145/2493123.2462921 – start-page: 111 volume-title: OpenACC to Intel Offload: Automatic Translation and Optimization year: 2013 ident: e_1_2_8_21_1 – volume-title: Intel Xeon Phi Coprocessor High‐Performance Programming year: 2013 ident: e_1_2_8_5_1 – ident: e_1_2_8_15_1 – ident: e_1_2_8_14_1 doi: 10.1109/IPDPSW.2013.179 – ident: e_1_2_8_9_1 – ident: e_1_2_8_23_1 doi: 10.1109/IPDPS.2013.113 – ident: e_1_2_8_24_1 doi: 10.1145/2484762.2484779 – ident: e_1_2_8_6_1 doi: 10.1109/HOTCHIPS.2012.7476487 – ident: e_1_2_8_4_1 – ident: e_1_2_8_7_1 – volume-title: Porting to the Intel Xeon Phi: Opportunities and Challenges year: 2013 ident: e_1_2_8_12_1 – ident: e_1_2_8_22_1 doi: 10.1109/IPDPS.2013.44 |
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Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge,... Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. To shed some light on the upcoming software challenge, this... |
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| SubjectTerms | Clusters Computation Computer programs Coprocessors hybrid programming Intel Xeon Phi coprocessor offload model Programming SCIF Sheds Symmetry Three dimensional Tianhe-2 |
| Title | Communication-hiding programming for clusters with multi-coprocessor nodes |
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