Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit c...

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Vydáno v:	Chronic diseases and translational medicine Ročník 13; číslo 4; s. 273 - 281
Hlavní autoři:	Wang, Yuan, Trefzer, Martin A, Bale, Simon J, Walker, James A, Tyrrell, Andy M
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Beijing The Institution of Engineering and Technology 01.07.2019 John Wiley & Sons, Inc
Témata:	Algorithms Bandwidths Circuits CLB input bandwidth constraints CLB utilisation configurable logic blocks Critical path electronic design automation field programmable gate array Field programmable gate arrays Flexibility flexible EDA flow FPGA CAD flow FPGA‐related literature genetic algorithms Golden 20 MCNC benchmark circuits integrated circuit design interconnect minimisation logic design Methods multiobjective genetic algorithm multiobjective optimisation algorithm network routing place‐and‐route process real‐world circuit design Research Article time optimising circuit performance parameters timing circuits timing driven circuit clustering interconnect minimisation field programmable gate arrays network routing FPGA-related literature genetic algorithms time optimising circuit performance parameters configurable logic blocks Golden 20 MCNC benchmark circuits field programmable gate array real-world circuit design CLB utilisation integrated circuit design flexible EDA flow timing driven circuit clustering multiobjective optimisation algorithm CLB input bandwidth constraints electronic design automation FPGA CAD flow place-and-route process multiobjective genetic algorithm logic design timing circuits
ISSN:	1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
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Shrnutí:	Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors’ new approach has been validated using the ‘Golden 20’ MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1751-8601 1751-861X 2095-882X 1751-861X 2589-0514
DOI:	10.1049/iet-cdt.2018.5115