Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit c...

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Vydáno v:	Chronic diseases and translational medicine Ročník 13; číslo 4; s. 273 - 281
Hlavní autoři:	Wang, Yuan, Trefzer, Martin A, Bale, Simon J, Walker, James A, Tyrrell, Andy M
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Beijing The Institution of Engineering and Technology 01.07.2019 John Wiley & Sons, Inc
Témata:	Algorithms Bandwidths Circuits CLB input bandwidth constraints CLB utilisation configurable logic blocks Critical path electronic design automation field programmable gate array Field programmable gate arrays Flexibility flexible EDA flow FPGA CAD flow FPGA‐related literature genetic algorithms Golden 20 MCNC benchmark circuits integrated circuit design interconnect minimisation logic design Methods multiobjective genetic algorithm multiobjective optimisation algorithm network routing place‐and‐route process real‐world circuit design Research Article time optimising circuit performance parameters timing circuits timing driven circuit clustering interconnect minimisation field programmable gate arrays network routing FPGA-related literature genetic algorithms time optimising circuit performance parameters configurable logic blocks Golden 20 MCNC benchmark circuits field programmable gate array real-world circuit design CLB utilisation integrated circuit design flexible EDA flow timing driven circuit clustering multiobjective optimisation algorithm CLB input bandwidth constraints electronic design automation FPGA CAD flow place-and-route process multiobjective genetic algorithm logic design timing circuits
ISSN:	1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
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Abstract	Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors’ new approach has been validated using the ‘Golden 20’ MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance.
AbstractList	Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place‐and‐route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g. power and delay. In this study, the authors present a method based on multi‐objective genetic algorithm (MOGA) to facilitate circuit clustering. They address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. The authors’ new approach has been validated using the ‘Golden 20’ MCNC benchmark circuits that are regularly used in FPGA‐related literature. The results show that the method proposed in this study achieves improvements of up to 50% in clustering, routability and timing when compared to state‐of‐the‐art approaches including VPack, T‐VPack, RPack, DPack, HDPack, MOPack and iRAC. The key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real‐world circuit design on FPGA, providing device utilisation at increased design performance.
Author	Walker, James A Trefzer, Martin A Wang, Yuan Tyrrell, Andy M Bale, Simon J
Author_xml	– sequence: 1 givenname: Yuan surname: Wang fullname: Wang, Yuan email: y.wang54@herts.ac.uk organization: 1School of Engineering and Technology, University of Hertfordshire, Hatfield, UK – sequence: 2 givenname: Martin A orcidid: 0000-0002-6196-6832 surname: Trefzer fullname: Trefzer, Martin A organization: 2Department of Electronic Engineering, University of York, York, UK – sequence: 3 givenname: Simon J surname: Bale fullname: Bale, Simon J organization: 2Department of Electronic Engineering, University of York, York, UK – sequence: 4 givenname: James A surname: Walker fullname: Walker, James A organization: 2Department of Electronic Engineering, University of York, York, UK – sequence: 5 givenname: Andy M surname: Tyrrell fullname: Tyrrell, Andy M organization: 2Department of Electronic Engineering, University of York, York, UK
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Cites_doi	10.1109/4235.996017 10.1109/FPL.2007.4380635 10.1109/FPT.2012.6412103 10.1145/2024724.2024908 10.1109/RECONFIG.2005.23 10.1561/1000000005 10.1109/ICES.2014.7008729 10.1109/SPL.2009.4914896 10.1613/jair.2106 10.1109/4235.585888 10.1109/T-C.1971.223159 10.7551/mitpress/1090.001.0001 10.1145/296399.296426 10.1007/3-540-45356-3_84 10.1109/ICEC.1994.350037 10.1109/CICC.1997.606687 10.1145/1331897.1331902 10.1109/CICC.2003.1249357 10.1109/ICCAD.2006.320013 10.1145/309847.309954 10.1145/503048.503058 10.1145/370155.370567 10.1109/4.75006 10.1162/evco.1994.2.3.221 10.1142/S0218126604001222 10.1007/978-1-4615-5145-4_3 10.1007/3-540-63465-7_226 10.1162/evco.1994.2.2.123 10.1145/611817.611821 10.1007/3-540-44719-9_20
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Keywords	interconnect minimisation field programmable gate arrays network routing FPGA-related literature genetic algorithms time optimising circuit performance parameters configurable logic blocks Golden 20 MCNC benchmark circuits field programmable gate array real-world circuit design CLB utilisation integrated circuit design flexible EDA flow timing driven circuit clustering multiobjective optimisation algorithm CLB input bandwidth constraints electronic design automation FPGA CAD flow place-and-route process multiobjective genetic algorithm logic design timing circuits
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Snippet	Circuit clustering algorithms fit synthesised circuits into field programmable gate array (FPGA) configurable logic blocks (CLBs) efficiently. This fundamental...
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SubjectTerms	Algorithms Bandwidths Circuits CLB input bandwidth constraints CLB utilisation configurable logic blocks Critical path electronic design automation field programmable gate array Field programmable gate arrays Flexibility flexible EDA flow FPGA CAD flow FPGA‐related literature genetic algorithms Golden 20 MCNC benchmark circuits integrated circuit design interconnect minimisation logic design Methods multiobjective genetic algorithm multiobjective optimisation algorithm network routing place‐and‐route process real‐world circuit design Research Article time optimising circuit performance parameters timing circuits timing driven circuit clustering
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Title	Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs
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