A Survey and Evaluation of FPGA High-Level Synthesis Tools

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to spec...

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Vydáno v:	IEEE transactions on computer-aided design of integrated circuits and systems Ročník 35; číslo 10; s. 1591 - 1604
Hlavní autoři:	Nane, Razvan, Sima, Vlad-Mihai, Pilato, Christian, Jongsok Choi, Fort, Blair, Canis, Andrew, Yu Ting Chen, Hsuan Hsiao, Brown, Stephen, Ferrandi, Fabrizio, Anderson, Jason, Bertels, Koen
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.10.2016 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Bambu comparison Dwarv evaluation Field programmable gate arrays field-programmable gate array (FPGA) Hardware Hardware design languages high-level synthesis (HLS) LegUp Optimization Program processors survey Yttrium
ISSN:	0278-0070, 1937-4151
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