Nane, R., Sima, V., Pilato, C., Choi, J., Fort, B., Canis, A., . . . Bertels, K. (2016). A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE transactions on computer-aided design of integrated circuits and systems, 35(10), 1591-1604. https://doi.org/10.1109/TCAD.2015.2513673
Citace podle Chicago (17th ed.)Nane, Razvan, et al. "A Survey and Evaluation of FPGA High-Level Synthesis Tools." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 35, no. 10 (2016): 1591-1604. https://doi.org/10.1109/TCAD.2015.2513673.
Citace podle MLA (9th ed.)Nane, Razvan, et al. "A Survey and Evaluation of FPGA High-Level Synthesis Tools." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 35, no. 10, 2016, pp. 1591-1604, https://doi.org/10.1109/TCAD.2015.2513673.