Efficient parallel implementation of three-point viterbi decoding algorithm on CPU, GPU, and FPGA
SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐poi...
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| Vydané v: | Concurrency and computation Ročník 26; číslo 3; s. 821 - 840 |
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10.03.2014
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| Abstract | SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley & Sons, Ltd. |
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| AbstractList | In wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley & Sons, Ltd. SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three‐point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace‐back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi‐core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145 × speedup over the naive CPU version on a quad‐core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65 Mbps and 12 × speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7 × speedup over Intel quad‐core CPU i5‐2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix‐4 pipelined architecture for the TVDA in a 45‐nm FPGA chip from Xilinx (XC6VLX760). Under 209.15‐MHz clock rate, it achieves a throughput of 418.30 Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real‐time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright © 2013 John Wiley & Sons, Ltd. In wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G communications. However, the throughput of Viterbi decoder is constrained by the convolutional characteristic. Recently, the three-point VDA (TVDA) was proposed to solve this problem. In TVDA, the whole procedure can be divided into three phases, the forward, trace-back, and decoding phases. In this paper, we analyze the parallelism of TVDA and propose parallel TVDA on the multi-core CPU, graphics processing unit (GPU), and field programmable gate array (FPGA). We demonstrate approaches that fully exploit its performance potential on CPU, GPU, and FPGA computing platforms. For CPU platforms, we perform two optimization methods, single instruction multiple data and multithreading to gain over 145speedup over the naive CPU version on a quad-core CPU platform. For GPU platforms, we propose the combination of cached memory optimization, coalesced global memory accesses, codeword packing scheme, and asynchronous data transition, achieving the throughput of 404.65Mbps and 12speedup over initial GPU versions on an NVIDIA GeForce GTX580 card and 7speedup over Intel quad-core CPU i5-2300, under the same manufacturing year and both with fully optimized schemes. In addition, for FPGA platforms, we customize a radix-4 pipelined architecture for the TVDA in a 45-nm FPGA chip from Xilinx (XC6VLX760). Under 209.15-MHz clock rate, it achieves a throughput of 418.30Mbps. Finally, we also discuss the performance evaluation and efficiency comparison of different flexible architectures for real-time Viterbi decoding in terms of the decoding throughput, power consumption, optimization schemes, programming costs, and price costs.Copyright copyright 2013 John Wiley & Sons, Ltd. |
| Author | Zou, Dan Dou, Yong Li, Rongchun |
| Author_xml | – sequence: 1 givenname: Rongchun surname: Li fullname: Li, Rongchun email: Correspondence to: Rongchun Li, National Laboratory for Parallel and Distribution Processing, National University of Defense Technology, Changsha, China., rongchunli@nudt.edu.cn organization: National Laboratory for Parallel and Distribution Processing, National University of Defense Technology, Changsha, China – sequence: 2 givenname: Yong surname: Dou fullname: Dou, Yong organization: National Laboratory for Parallel and Distribution Processing, National University of Defense Technology, Changsha, China – sequence: 3 givenname: Dan surname: Zou fullname: Zou, Dan organization: National Laboratory for Parallel and Distribution Processing, National University of Defense Technology, Changsha, China |
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| Cites_doi | 10.4218/etrij.08.0208.0196 10.1109/MCOM.2010.5434388 10.1109/TIT.1967.1054010 10.1109/VTCF.2006.176 10.1109/ICCT.2006.341948 10.1109/PROC.1973.9030 10.1109/ICISE.2009.265 10.1007/s10470-011-9764-9 10.1109/26.221067 10.1007/978-3-642-11515-8_26 10.1109/wicom.2011.6036680 10.1109/WCSP.2011.6096781 10.1109/TVLSI.2004.842930 10.1109/SOCDC.2009.5423923 10.1109/SIPS.2009.5336249 10.1002/cpe.1913 10.1109/ICEEE.2006.251908 |
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| References_xml | – reference: Mesmay FD, Chellappa S, Franchetti F, Markus P. Computer generation of efficient software Viterbi decoders. Lecture Notes in Computer Science 2010; 5952:353-368. – reference: Viterbi AJ. Error bounds for convolutional codes and asymptoticaIly optimum decoding algorithm. IEEE Transactions on Information Theory 1967; IT-13(4):260-269. – reference: Ahn C, Kim J, Ju J, Choi J, Choi B, Choi S. Implementation of an SDR platform using GPU and its application to a 2 × 2 MIMO WiMAX system. Analog Integrated Circuits and Signal Processing 2011; 69(2):107-117. – reference: Choi SW, Kang KM, Choi SS. A Two-stage radix-4 Viterbi decoder for multiband OFDM UWB system. ETRI Journal 2008; 30(6):850-852. – reference: Forney GD. The Viterbi algorithm. Proceedings of the IEEE 1973; 61(3):268-278. – reference: Tessier R, Swaminathan S, Ramaswamy R, Goeckel D, Burleson W. A reconfigurable, power-efficient adaptive Viterbi decoder. IEEE Transactions on Very Large Scale Integration VLSI Systems 2005; 13(4):484-488. – reference: Feygin G, Gulak PG. Architectural tradeoffs for survivor sequence memory management in Viterbi decoders. IEEE Transactions on Communications 1993; 41(3):425-429. – reference: Kim J, Seungheon H, Seungwon C. Implementation of an SDR system using graphics processing unit. IEEE Communications Magazine 2010; 48(3):156-162. – reference: Zou D, Dou Y, Xia F. Optimization schemes and performance evaluation of Smith-Waterman algorithm on CPU, GPU and FPGA. Concurrency and Computation-Practice & Experience 2012; 24(14):1625-1644. – start-page: 1 year: 2007 end-page: 4 – start-page: 185 year: 2009 end-page: 190 – volume: 5952 start-page: 353 year: 2010 end-page: 368 article-title: Computer generation of efficient software Viterbi decoders publication-title: Lecture Notes in Computer Science – volume: IT‐13 start-page: 260 issue: 4 year: 1967 end-page: 269 article-title: Error bounds for convolutional codes and asymptoticaIly optimum decoding algorithm publication-title: IEEE Transactions on Information Theory – year: 2005 – volume: 24 start-page: 1625 issue: 14 year: 2012 end-page: 1644 article-title: Optimization schemes and performance evaluation of Smith–Waterman algorithm on CPU, GPU and FPGA publication-title: Concurrency and Computation‐Practice & Experience – volume: 69 start-page: 107 issue: 2 year: 2011 end-page: 117 article-title: Implementation of an SDR platform using GPU and its application to a 2 × 2 MIMO WiMAX system publication-title: Analog Integrated Circuits and Signal Processing – volume: 41 start-page: 425 issue: 3 year: 1993 end-page: 429 article-title: Architectural tradeoffs for survivor sequence memory management in Viterbi decoders publication-title: IEEE Transactions on Communications – start-page: 121 year: 2009 end-page: 124 – start-page: 51 year: 2006 end-page: 55 – start-page: 1 year: 2011 end-page: 4 – start-page: 1 year: 2006 end-page: 4 – start-page: 1 year: 2006 end-page: 5 – volume: 30 start-page: 850 issue: 6 year: 2008 end-page: 852 article-title: A Two‐stage radix‐4 Viterbi decoder for multiband OFDM UWB system publication-title: ETRI Journal – volume: 13 start-page: 484 issue: 4 year: 2005 end-page: 488 article-title: A reconfigurable, power‐efficient adaptive Viterbi decoder publication-title: IEEE Transactions on Very Large Scale Integration VLSI Systems – start-page: 468 year: 2009 end-page: 471 – start-page: 1 year: 2011 end-page: 6 – start-page: 237 year: 2007 end-page: 241 – volume: 61 start-page: 268 issue: 3 year: 1973 end-page: 278 article-title: The Viterbi algorithm publication-title: Proceedings of the IEEE – volume: 48 start-page: 156 issue: 3 year: 2010 end-page: 162 article-title: Implementation of an SDR system using graphics processing unit publication-title: IEEE Communications Magazine – ident: e_1_2_8_5_1 – ident: e_1_2_8_23_1 doi: 10.4218/etrij.08.0208.0196 – ident: e_1_2_8_8_1 doi: 10.1109/MCOM.2010.5434388 – ident: e_1_2_8_2_1 doi: 10.1109/TIT.1967.1054010 – ident: e_1_2_8_6_1 – ident: e_1_2_8_11_1 – ident: e_1_2_8_16_1 doi: 10.1109/VTCF.2006.176 – ident: e_1_2_8_17_1 – ident: e_1_2_8_19_1 – ident: e_1_2_8_18_1 doi: 10.1109/ICCT.2006.341948 – ident: e_1_2_8_3_1 doi: 10.1109/PROC.1973.9030 – ident: e_1_2_8_13_1 doi: 10.1109/ICISE.2009.265 – ident: e_1_2_8_9_1 doi: 10.1007/s10470-011-9764-9 – ident: e_1_2_8_10_1 doi: 10.1109/26.221067 – ident: e_1_2_8_12_1 doi: 10.1007/978-3-642-11515-8_26 – ident: e_1_2_8_14_1 doi: 10.1109/wicom.2011.6036680 – ident: e_1_2_8_22_1 doi: 10.1109/WCSP.2011.6096781 – ident: e_1_2_8_4_1 doi: 10.1109/TVLSI.2004.842930 – ident: e_1_2_8_21_1 doi: 10.1109/SOCDC.2009.5423923 – ident: e_1_2_8_20_1 doi: 10.1109/SIPS.2009.5336249 – ident: e_1_2_8_24_1 doi: 10.1002/cpe.1913 – ident: e_1_2_8_7_1 – ident: e_1_2_8_15_1 doi: 10.1109/ICEEE.2006.251908 |
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| Snippet | SUMMARYIn wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX,... In wireless communication, Viterbi decoding algorithm (VDA) is the one of most popular channel decoding algorithms, which is widely used in WLAN, WiMAX, or 3G... |
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| SubjectTerms | Algorithms Central processing units CUDA Decoding Field programmable gate arrays FPGA GPU OpenMP Optimization Platforms SDR SSE viterbi Viterbi decoding Wireless communication |
| Title | Efficient parallel implementation of three-point viterbi decoding algorithm on CPU, GPU, and FPGA |
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