Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach
Summary The development of applications for high‐performance embedded systems is a long and error‐prone process because in addition to the required functionality, developers must consider various and often conflicting nonfunctional requirements such as performance and/or energy efficiency. The compl...
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| Vydané v: | Software, practice & experience Ročník 46; číslo 2; s. 251 - 287 |
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| Hlavní autori: | , , , , , , |
| Médium: | Journal Article |
| Jazyk: | English |
| Vydavateľské údaje: |
Bognor Regis
Blackwell Publishing Ltd
01.02.2016
Wiley Subscription Services, Inc |
| Predmet: | |
| ISSN: | 0038-0644, 1097-024X |
| On-line prístup: | Získať plný text |
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| Shrnutí: | Summary
The development of applications for high‐performance embedded systems is a long and error‐prone process because in addition to the required functionality, developers must consider various and often conflicting nonfunctional requirements such as performance and/or energy efficiency. The complexity of this process is further exacerbated by the multitude of target architectures and mapping tools. This article describes LARA, an aspect‐oriented programming language that allows programmers to convey domain‐specific knowledge and nonfunctional requirements to a toolchain composed of source‐to‐source transformers, compiler optimizers, and mapping/synthesis tools. LARA is sufficiently flexible to target different tools and host languages while also allowing the specification of compilation strategies to enable efficient generation of software code and hardware cores (using hardware description languages) for hybrid target architectures – a unique feature to the best of our knowledge not found in any other aspect‐oriented programming language. A key feature of LARA is its ability to deal with different models of join points, actions, and attributes. In this article, we describe the LARA approach and evaluate its impact on code instrumentation and analysis and on selecting critical code sections to be migrated to hardware accelerators for two embedded applications from industry. Copyright © 2014 John Wiley & Sons, Ltd. |
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| Bibliografia: | ArticleID:SPE2301 FP7 - No. 257906; No. 287804; No. 318521 istex:CA33DFEE17C7DB9BCBD5B3C8F069B463A8F40DC6 REFLECT European Community - No. 248976 Portuguese Science Foundation (FCT) - No. SFRH/BD/90507/2012 UK EPSRC ark:/67375/WNG-WG9LD9LT-J ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 |
| ISSN: | 0038-0644 1097-024X |
| DOI: | 10.1002/spe.2301 |