Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures

A large portion of existing multithreaded embedded software has been programmed according to symmetric shared memory platforms where a monolithic memory block is shared by all cores. Such platforms accommodate popular parallel programming models such as POSIX threads and OpenMP. However with the gro...

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Bibliographic Details
Published in:IEEE transactions on computers Vol. 65; no. 8; pp. 2645 - 2651
Main Authors: Garibotti, Rafael, Butko, Anastasiia, Ost, Luciano, Gamatie, Abdoulaye, Sassatelli, Gilles, Adeniyi-Jones, Chris
Format: Journal Article
Language:English
Published: New York IEEE 01.08.2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Institute of Electrical and Electronics Engineers
Subjects:
Architecture
Architecture (computers)
Coherence
Computer Science
Distributed memory
distributed shared memory
Embedded computer systems
Embedded Systems
Hardware
Hardware Architecture
Instruction sets
Mathematical models
Migration
Multicore processing
Multicore programmability
performance scalability
Platforms
Programming
Software Engineering
software migration
Programming
Hardware
Multicore processing
Instruction sets
Coherence
ISSN:0018-9340, 1557-9956
Online Access:Get full text
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Summary:A large portion of existing multithreaded embedded software has been programmed according to symmetric shared memory platforms where a monolithic memory block is shared by all cores. Such platforms accommodate popular parallel programming models such as POSIX threads and OpenMP. However with the growing number of cores in modern manycore embedded architectures, they present a bottleneck related to their centralized memory accesses. This paper proposes a solution tailored for an efficient execution of applications defined with shared-memory programming models onto on-chip distributed-memory multicore architectures. It shows how performance, area and energy consumption are significantly improved thanks to the scalability of these architectures. This is illustrated in an open-source realistic design framework, including tools from ASIC to microkernel.
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2015.2485202