An implementation of fuzzy logic controller on the reconfigurable FPGA system
This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on t...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on industrial electronics (1982) Jg. 47; H. 3; S. 703 - 715 |
|---|---|
| 1. Verfasser: | |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
IEEE
01.06.2000
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 0278-0046, 1557-9948 |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Abstract | This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. Each implemented module forms a downloadable hardware object that is ready to configure the FPGA chip. Then, the FPGA chip is consequently reconfigured with one module at a time by using the run-time reconfiguration method. This implementation method is effective when a single FPGA chip cannot fit the FLC due to the limited size of its constituent cells. We test the proposed implementation method by building the FLC for the truck backer-upper control on VCC Corporation's EVC-1 reconfigurable FPGA board directly. |
|---|---|
| AbstractList | In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. Each implemented module forms a downloadable hardware object that is ready to configure the FPGA chip. Then, the FPGA chip is consequently reconfigured with one module at a time by using the run-time reconfiguration method. This implementation method is effective when a single FPGA chip cannot fit the FLC due to the limited size of its constituent cells. We test the proposed implementation method by building the FLC for the truck backer-upper control on VCC Corporation's EVC-1 reconfigurable FPGA board directly This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually on the FLC automatic design and implementation system, which is an integrated development environment for performing many subtasks such as automatic VHSIC hardware description language description, FPGA synthesis, optimization, placement and routing, and downloading. Each implemented module forms a downloadable hardware object that is ready to configure the FPGA chip. Then, the FPGA chip is consequently reconfigured with one module at a time by using the run-time reconfiguration method. This implementation method is effective when a single FPGA chip cannot fit the FLC due to the limited size of its constituent cells. We test the proposed implementation method by building the FLC for the truck backer-upper control on VCC Corporation's EVC-1 reconfigurable FPGA board directly. |
| Author | Daijin Kim |
| Author_xml | – sequence: 1 givenname: Daijin surname: Kim fullname: Kim, Daijin |
| BookMark | eNqF0TFP3TAQB3ALUYkHZejayWJo1SHgi-3YHp-egCJRtUOZIz_nDEZO_Gonw-PTExTUAVVlsuz73enk_zE5HNKAhHwCdg7AzIWAcy2UATggK5BSVcYIfUhWrFa6Ykw0R-S4lEfGQEiQK_JjPdDQ7yL2OIx2DGmgyVM_PT3taUz3wVGXhjGnGDHTuTg-IM04v_lwP2W7jUivfl2vadmXEfuP5IO3seDp63lC7q4uf2--V7c_r28269vKcaPHyjGtdKc4yA65sFpxVHILKCwD1Xm1bSTOd-86X6MG3QnuOXPWSMNR-pqfkK_L3F1OfyYsY9uH4jBGO2CaSmtANJypRs_yy39lbQRADeJ9qEXN513eh0oqxuTLxLM38DFNeZj_pdVaMiFZo2Z0sSCXUykZfevCksOYbYgtsPYl11ZAu-Q6d3x707HLobd5_0_7ebEBEf-61-IzmvSq_g |
| CODEN | ITIED6 |
| CitedBy_id | crossref_primary_10_1007_s40435_021_00875_4 crossref_primary_10_1016_j_comcom_2004_07_009 crossref_primary_10_20965_jaciii_2008_p0348 crossref_primary_10_1109_TIE_2008_2007040 crossref_primary_10_1049_ip_epa_20050502 crossref_primary_10_1109_TII_2011_2123908 crossref_primary_10_1109_TII_2012_2211608 crossref_primary_10_3390_computation7040063 crossref_primary_10_1016_j_neucom_2007_10_026 crossref_primary_10_1007_s10776_004_7872_5 crossref_primary_10_1049_iet_epa_2008_0104 crossref_primary_10_3390_a11100146 crossref_primary_10_1016_j_isatra_2018_12_030 crossref_primary_10_1109_TFUZZ_2003_817841 crossref_primary_10_1109_TIE_2007_898281 crossref_primary_10_1109_TIE_2014_2312312 crossref_primary_10_1016_j_eswa_2014_05_032 crossref_primary_10_1109_61_997905 crossref_primary_10_1109_TCDS_2019_2932179 crossref_primary_10_1109_TFUZZ_2006_876735 crossref_primary_10_1109_ACCESS_2018_2836858 crossref_primary_10_1109_TMECH_2007_910054 crossref_primary_10_1016_j_sysarc_2018_06_005 crossref_primary_10_1109_5_949483 crossref_primary_10_1109_TSMCC_2010_2049262 crossref_primary_10_1109_TCAD_2018_2834436 crossref_primary_10_1049_ip_epa_20050205 crossref_primary_10_1007_s10776_006_0048_8 crossref_primary_10_1016_j_engappai_2014_02_008 crossref_primary_10_1109_TIE_2007_898299 crossref_primary_10_3390_s24237709 crossref_primary_10_1016_j_enconman_2011_01_021 crossref_primary_10_1109_TIE_2007_898292 crossref_primary_10_1016_j_micpro_2015_11_012 crossref_primary_10_1109_TIE_2003_817490 crossref_primary_10_3390_math9111164 crossref_primary_10_1155_2013_343174 crossref_primary_10_1177_1077546312449645 crossref_primary_10_1109_JBHI_2013_2279595 crossref_primary_10_1109_MAP_2012_6230771 crossref_primary_10_3233_JIFS_212411 crossref_primary_10_1109_TPEL_2008_924604 crossref_primary_10_1016_j_eswa_2015_04_050 crossref_primary_10_1109_TIE_2011_2161250 crossref_primary_10_1080_00207217_2015_1017844 crossref_primary_10_1109_JSEN_2008_917124 crossref_primary_10_1109_TPEL_2007_900553 crossref_primary_10_1016_j_ifacol_2015_07_026 crossref_primary_10_1049_cth2_12589 crossref_primary_10_1049_iet_epa_20070178 crossref_primary_10_1109_TIM_2008_925723 |
| Cites_doi | 10.1016/S0165-0114(97)00199-1 10.1007/978-1-4615-3216-3 10.1109/MEX.1986.4306980 10.1109/FUZZY.1992.258657 10.1109/91.544304 10.1109/41.753785 10.1109/40.476266 10.1109/91.277959 10.1109/91.544305 10.1109/21.199466 10.1109/TC.1986.1676734 10.1109/FUZZY.1992.258686 10.1007/978-1-4615-2742-8 10.1109/3468.553224 10.1109/91.544303 10.1007/3-540-60294-1_136 |
| ContentType | Journal Article |
| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2000 |
| Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2000 |
| DBID | RIA RIE AAYXX CITATION 7SP 8FD L7M 7U5 7TB FR3 F28 |
| DOI | 10.1109/41.847911 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace Solid State and Superconductivity Abstracts Mechanical & Transportation Engineering Abstracts Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
| DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts Solid State and Superconductivity Abstracts Mechanical & Transportation Engineering Abstracts Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
| DatabaseTitleList | Technology Research Database Engineering Research Database Technology Research Database Solid State and Superconductivity Abstracts Technology Research Database |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 1557-9948 |
| EndPage | 715 |
| ExternalDocumentID | 2434399281 10_1109_41_847911 847911 |
| GroupedDBID | -~X .DC 0R~ 29I 4.4 5GY 5VS 6IK 97E 9M8 AAJGR AARMG AASAJ AAWTH ABAZT ABQJQ ABVLG ACGFO ACGFS ACIWK ACKIV ACNCT AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD HZ~ H~9 IBMZZ ICLAB IFIPE IFJZH IPLJI JAVBF LAI M43 MS~ O9- OCL P2P RIA RIE RNS TAE TN5 TWZ VH1 VJK AAYXX CITATION 7SP 8FD L7M RIG 7U5 7TB FR3 F28 |
| ID | FETCH-LOGICAL-c398t-c0878d7315de34a873e75b1e4a017df7b65e5b1fcdf2e818d43f30ca9593e5f23 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 87 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000087695600023&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 0278-0046 |
| IngestDate | Thu Oct 02 11:02:21 EDT 2025 Sat Sep 27 21:34:52 EDT 2025 Sat Sep 27 21:46:29 EDT 2025 Sun Sep 28 06:07:42 EDT 2025 Mon Jun 30 10:15:08 EDT 2025 Sat Nov 29 03:59:52 EST 2025 Tue Nov 18 22:21:01 EST 2025 Tue Aug 26 21:00:24 EDT 2025 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 3 |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c398t-c0878d7315de34a873e75b1e4a017df7b65e5b1fcdf2e818d43f30ca9593e5f23 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 ObjectType-Article-2 ObjectType-Feature-1 content type line 23 |
| PQID | 885045067 |
| PQPubID | 23500 |
| PageCount | 13 |
| ParticipantIDs | proquest_miscellaneous_914630768 ieee_primary_847911 proquest_miscellaneous_27570054 proquest_journals_885045067 crossref_citationtrail_10_1109_41_847911 crossref_primary_10_1109_41_847911 proquest_miscellaneous_29411214 proquest_miscellaneous_28423818 |
| PublicationCentury | 2000 |
| PublicationDate | 2000-06-01 |
| PublicationDateYYYYMMDD | 2000-06-01 |
| PublicationDate_xml | – month: 06 year: 2000 text: 2000-06-01 day: 01 |
| PublicationDecade | 2000 |
| PublicationPlace | New York |
| PublicationPlace_xml | – name: New York |
| PublicationTitle | IEEE transactions on industrial electronics (1982) |
| PublicationTitleAbbrev | TIE |
| PublicationYear | 2000 |
| Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref13 ref12 ref15 hutchings (ref26) 1995 ref14 ref30 ref11 ref10 (ref20) 1996 ref2 ref17 ref16 takagi (ref1) 1993 casselman (ref27) 1995 (ref3) 1993 wang (ref28) 1991 (ref22) 1996 (ref5) 1992 ref23 ref25 (ref19) 1996 ref29 (ref18) 1996 ref8 (ref21) 1994 ref7 tasaka (ref9) 1989 ref6 hwang (ref24) 1984 (ref4) 1994 |
| References_xml | – ident: ref30 doi: 10.1016/S0165-0114(97)00199-1 – ident: ref17 doi: 10.1007/978-1-4615-3216-3 – ident: ref2 doi: 10.1109/MEX.1986.4306980 – year: 1992 ident: ref5 publication-title: Data Sheet MB94140 Series – ident: ref11 doi: 10.1109/FUZZY.1992.258657 – ident: ref13 doi: 10.1109/91.544304 – year: 1996 ident: ref20 publication-title: XactSstep Development System User Guide – year: 1984 ident: ref24 publication-title: Computer Architecture and Parallel Processing – ident: ref23 doi: 10.1109/41.753785 – ident: ref25 doi: 10.1109/40.476266 – ident: ref8 doi: 10.1109/91.277959 – year: 1993 ident: ref3 publication-title: Data Sheet NLX220 – year: 1994 ident: ref4 publication-title: Data Sheet W A R P 1 0 – ident: ref14 doi: 10.1109/91.544305 – year: 1993 ident: ref1 article-title: cooperative system of neural network, fuzzy logic and its application to consumer products publication-title: Industrial Applications of Fuzzy Control and Intelligent Systems – year: 1995 ident: ref27 publication-title: H O T (Hardware Object Technology) Programming Tutorial – year: 1991 ident: ref28 publication-title: Generating fuzzy rules from numerical data – start-page: 280 year: 1989 ident: ref9 article-title: hybrid bus type fuzzy controller with analog fuzzy chips publication-title: Proc IFSA World Congr – year: 1996 ident: ref19 publication-title: Design Compiler Reference Manual v3 4 – ident: ref29 doi: 10.1109/21.199466 – ident: ref7 doi: 10.1109/TC.1986.1676734 – year: 1996 ident: ref22 publication-title: The Programmable Logic Data Book – ident: ref10 doi: 10.1109/FUZZY.1992.258686 – ident: ref16 doi: 10.1007/978-1-4615-2742-8 – ident: ref15 doi: 10.1109/3468.553224 – year: 1994 ident: ref21 publication-title: EVC1 Virtual Computer Programming Tutorial – ident: ref12 doi: 10.1109/91.544303 – ident: ref6 doi: 10.1109/91.544305 – start-page: 419 year: 1995 ident: ref26 article-title: implementation approaches for reconfigurable logic applications publication-title: Proc 5th Int Workshop Field Programmable Logic and Applications doi: 10.1007/3-540-60294-1_136 – year: 1996 ident: ref18 publication-title: VSS Family Tutorial v3 4 |
| SSID | ssj0014515 |
| Score | 1.9931799 |
| Snippet | This paper concerns an implementation of a fuzzy logic controller (FLC) on a reconfigurable field-programmable gate array (FPGA) system. In the proposed... In the proposed implementation method, the FLC is partitioned into many temporally independent functional modules, and each module is implemented individually... |
| SourceID | proquest crossref ieee |
| SourceType | Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 703 |
| SubjectTerms | Automatic control Chips Constituents Control systems Design optimization Field programmable gate arrays Fuzzy control Fuzzy logic Hardware design languages Logic arrays Modules Routing Run time (computers) Runtime Very high speed integrated circuits |
| Title | An implementation of fuzzy logic controller on the reconfigurable FPGA system |
| URI | https://ieeexplore.ieee.org/document/847911 https://www.proquest.com/docview/885045067 https://www.proquest.com/docview/27570054 https://www.proquest.com/docview/28423818 https://www.proquest.com/docview/29411214 https://www.proquest.com/docview/914630768 |
| Volume | 47 |
| WOSCitedRecordID | wos000087695600023&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1557-9948 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0014515 issn: 0278-0046 databaseCode: RIE dateStart: 19820101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LT8MwDI5g4gAH3ogxHhHiwKXQLk6THCfE4MK0A0jcqrZx0CTo0LYisV9PkrYTiIfEqY84VeQ0sR3bnwk5YyxTRoYQ6DDSAYDhgVKYBqhEqmIwYFjmi02IwUA-PqphjbPtc2EQ0Qef4YW79b58Pc5Ld1R2aXdS5fJ4l4WIq1SthcMAeFWsoOsAY63NV4MIRaG6hOii6vhF9PhaKt82YC9V-hv_Gs8mWa-VR9qrZnuLLGGxTdY-QQrukLteQUcvTVC44zodG2rK-fyd-m2O1sHpzzihttHqf9QbxWb0VE5cHhXtD296tEJ43iUP_ev7q9ugLpkQ5EzJWZCHUkgtWMQ1MkilYCh4FiGkduVpI7KYo302uTZdtLJaAzMszFMHT4zcdNkeaRXjAvcJZRkoLTUHkTHgucxk6i62q450BnGbnDfcTPIaT9yVtXhOvF0RqgSipOJQm5wuSF8rEI2fiLYdhxcEzdtOM0NJvbqmiZTcaqJWzrbJyaLVLgvn60gLHJfTpCsccD-HPygkeHXlDwoFVhuN7DfoLxTKyhnmfJkHPw6-Q1arzH13aHNIWrNJiUdkJX-bjaaTY_8DfwDW3fCV |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3dS8MwEA-igvrgtzjnRxAffKm2zWVJHoc4J-rwQcG30jYXGWgn2yroX2-SdkPxA3zqRy4lXJrcXe7ud4QcMZYpI0MIdBjpAMDwQClMA1QiVS0wYFjmi02IXk8-PKjbGmfb58Igog8-wxN36335epCX7qjs1O6kyuXxznGAOKyStaYuA-BVuYLYQcZaq6-GEYpCdQrRSdX1i_Dx1VS-bcFernRW_jWiVbJcq4-0Xc33GpnBYp0sfQIV3CA37YL2nydh4Y7vdGCoKd_f36jf6Ggdnv6EQ2obrQZIvVls-o_l0GVS0c7tRZtWGM-b5L5zfnfWDeqiCUHOlBwHeSiF1IJFXCODVAqGgmcRQmrXnjYia3G0zybXJkYrrTUww8I8dQDFyE3MtshsMShwm1CWgdJScxAZA57LTKbuYrvqSGfQapDjCTeTvEYUd4UtnhJvWYQqgSipONQgh1PSlwpG4yeidcfhKcHkbXMyQ0m9vkaJlNzqolbSNsjBtNUuDOftSAsclKMkFg66n8MfFBK8wvIHhQKrj0b2G_QXCmUlDXPezJ0fB39AFrp3N9fJ9WXvqkkWqzx-d4SzS2bHwxL3yHz-Ou6Phvv-Z_4AeOvz3A |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=An+implementation+of+fuzzy+logic+controller+on+the+reconfigurable+FPGA+system&rft.jtitle=IEEE+transactions+on+industrial+electronics+%281982%29&rft.au=Kim%2C+Daijin&rft.date=2000-06-01&rft.issn=0278-0046&rft.volume=47&rft.issue=3&rft.spage=703&rft.epage=715&rft_id=info:doi/10.1109%2F41.847911&rft.externalDBID=NO_FULL_TEXT |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0278-0046&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0278-0046&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0278-0046&client=summon |