A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash

For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this arti...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems Jg. 41; H. 6; S. 1971 - 1975
Hauptverfasser:	Cui, Lanlan, Liu, Xiaojian, Wu, Fei, Lu, Zhonghai, Xie, Changsheng
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.06.2022 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Algorithms Binary system Bit error rate Bit-width Codes Complexity Decoding Decoding algorithm Decoding performance Economic and social effects Error correcting codes Error correction Flash memory Flash memory (computers) Hardware Implementation complexity Iterative decoding Likelihood ratio Log likelihood ratios (LLR) Low density parity check decoding low-density parity-check (LDPC) codes Manganese Memory architecture min-sum decoding NAND circuits NAND flash memory Normalized min-sum algorithms Quasi-cyclic LDPC (QC-LDPC) Reliability Throughput Uncorrectable bit error rates
ISSN:	0278-0070, 1937-4151, 1937-4151
Online-Zugang:	Volltext
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