APA (7th ed.) Citation

Cui, L., Liu, X., Wu, F., Lu, Z., & Xie, C. (2022). A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash. IEEE transactions on computer-aided design of integrated circuits and systems, 41(6), 1971-1975. https://doi.org/10.1109/TCAD.2021.3100273

Chicago Style (17th ed.) Citation

Cui, Lanlan, Xiaojian Liu, Fei Wu, Zhonghai Lu, and Changsheng Xie. "A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems 41, no. 6 (2022): 1971-1975. https://doi.org/10.1109/TCAD.2021.3100273.

MLA (9th ed.) Citation

Cui, Lanlan, et al. "A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash." IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 41, no. 6, 2022, pp. 1971-1975, https://doi.org/10.1109/TCAD.2021.3100273.