Automatic CNN Model Partitioning for GPU/FPGA-based Embedded Heterogeneous Accelerators using Geometric Programming

Graphics Processing Unit (GPU), dedicated Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) accelerators are currently platforms of choice for porting Convolutional Neural Networks (CNNs). In this work, an automated Central Processing Unit (CPU)-GPU-FPGA partiti...

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Bibliographic Details
Published in:	Journal of signal processing systems Vol. 95; no. 10; pp. 1203 - 1218
Main Authors:	Carballo-Hernández, Walther, Pelcat, Maxime, Berry, François
Format:	Journal Article
Language:	English
Published:	New York Springer US 01.10.2023 Springer Nature B.V Springer
Subjects:	Accelerators Application specific integrated circuits Artificial neural networks Central processing units Circuits and Systems Co-design Communication Computer Imaging Computer Science Constraints Convexity CPUs Deep learning Design optimization Electrical Engineering Embedded systems Energy consumption Engineering Field programmable gate arrays Graphics processing units Image Processing and Computer Vision Linear programming Mathematical programming Optimization techniques Partitioning Pattern Recognition Pattern Recognition and Graphics Performance measurement Polynomials Signal,Image and Speech Processing Tiling Vision Workloads Convolutional Neural Network Embedded design Heterogeneous platform Mathematical optimization Geometric programming
ISSN:	1939-8018, 1939-8115
Online Access:	Get full text
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