Automating functional unit and register binding for synchoros CGRA platform

Coarse-grain reconfigurable architectures, which provide high computing throughput, low cost, scalability, and energy efficiency, have grown in popularity in recent years. SiLago is a new VLSI design framework comprised of two coarse-grain reconfigurable fabrics: a dynamically reconfigurable resourc...

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Bibliographic Details
Published in:Design automation for embedded systems Vol. 28; no. 2; pp. 155 - 186
Main Authors: Pudi, Dhilleswararao, Tiwari, Utsav, Boppu, Srinivas, Yang, Yu, Hemani, Ahmed
Format: Journal Article
Language:English
Published: New York Springer US 01.06.2024
Springer
Springer Nature B.V
Subjects:
Algorithms
Architecture
Automation
Binding
CAE) and Design
Circuits and Systems
Coarse-grain reconfigurable architecture
Computer-Aided Engineering (CAD
Design
Designers
Distributed memory
Distributed memory architecture
Dynamically reconfigurable resource array
Energy dissipation
Energy efficiency
Engineering
Fabrics
High level synthesis
Image processing
Integer linear programming
Integer programming
Linear algebra
Linear programming
Macros
Mechanization
Network latency
Performance measurement
Power management
Reconfiguration
Signal processing
SiLago
Special Purpose and Application-Based Systems
Technology application
Very-large-scale integration
Vesyla
Binding
High-level synthesis
Dynamically reconfigurable resource array
Integer linear programming
Distributed memory architecture
Vesyla
Coarse-grain reconfigurable architecture
SiLago
ISSN:0929-5585, 1572-8080, 1572-8080
Online Access:Get full text
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Summary:Coarse-grain reconfigurable architectures, which provide high computing throughput, low cost, scalability, and energy efficiency, have grown in popularity in recent years. SiLago is a new VLSI design framework comprised of two coarse-grain reconfigurable fabrics: a dynamically reconfigurable resource array and a distributed memory architecture. It employs the Vesyla compiler to map streaming applications on these fabrics. Binding is a critical step in the high-level synthesis that maps operations and variables to functional units and storage elements in the design. It influences design performance metrics such as power, latency, area, etc. The current version of Vesyla does not support automatic binding, and it has to be specified manually through pragmas, which makes it less flexible. This paper proposes various approaches to automate the binding in Vesyla. We present a list scheduling-based approach to automate functional unit binding and an integer linear programming approach to automate register binding. Furthermore, we determine the binding of various basic linear algebraic subprogram and image processing tasks using the proposed approaches. Finally, a comparative analysis has been made between the automatic and manual binding concerning the power dissipation and latency for various benchmarks. The experimental results show that the proposed automatic binding consumes significantly less power for nearly the same latency as manual binding.
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ISSN:0929-5585
1572-8080
1572-8080
DOI:10.1007/s10617-024-09286-y