Design methodology for a modular service-driven network processor architecture

We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of...

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Vydáno v:	Computer networks (Amsterdam, Netherlands : 1999) Ročník 41; číslo 5; s. 623 - 640
Hlavní autoři:	Gabrani, Maria, Dittmann, Gero, Döring, Andreas, Herkersdorf, Andreas, Sagmeister, Patricia, van Lunteren, Jan
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Amsterdam Elsevier B.V 05.04.2003 Elsevier Sequoia S.A
Témata:	Architecture Methods Microprocessors Modular and scalable architectures Network processors Networking Networks Open systems Performance evaluation Scalability Studies Systems on a chip Task performance Systems on a chip Performance evaluation Network processors Modular and scalable architectures Open systems
ISSN:	1389-1286, 1872-7069
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Abstract	We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system.
AbstractList	We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system. A design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors is presented. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. The rationale behind the selected functional partitioning in hardware and software components is described and the challenges of designing the hardware components, and of organizing and integrating the programmable cores, are discussed. The approach is quantified with a performance evaluation of the overall system. Article included in a special issue devoted to the theme: Network processors. Presents a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. Describes the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. Quantifies the approach with a performance evaluation of the overall system. (Original abstract)
Author	Gabrani, Maria van Lunteren, Jan Herkersdorf, Andreas Sagmeister, Patricia Dittmann, Gero Döring, Andreas
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References_xml	– reference: J.A. Nestor, V. Tamas, Exploiting scheduling freedom in controller synthesis, in: Proceedings of 6th International Workshop on High-Level Synthesis, November 1992, pp. 74–86 – reference: G. Dittmann, Programmable Finite State Machines for High-speed Communication Components, Master’s Thesis, Darmstadt University of Technology, 2000. Available from < – year: 1994 ident: BIB15 article-title: Specification and Design of Embedded Systems – reference: RFC 2475, An Architecture for Differentiated Services, S. Blake et al., December 1998 – reference: C. Jenkins, NPU co-processors, the power to process, Presentation at Network Processor Conference, August 2000 – reference: EZchip Technologies Ltd., Network Processor Designs for Next-Generation Networking Equipment, White Paper, 1999 – reference: Texas Instruments Incorporated, TMS320C80 Digital Signal Processor Data Sheet 2000 – reference: P. Crowley, J.-L. Baer, A modeling framework for network processor systems, in: Proceedings of 8th International Symposium on High-Performance Computer Architectures; Workshop on Network Processors, Cambridge, MA, February 3, 2002 – reference: E. Bowen, C. Jeffries, L. Kencl, A. Kind, R. Pletka, Bandwidth allocation for non-responsive flows with active queue management, in: Proceedings of International Zurich Seminar on Broadband Communications, Zurich, 2002 – reference: draft-ietf-diffserv-model-06.txt, An Informal Management Model for Diffserv Routers, Y. Bernet, S. Blake, A. Smith, February, 2001 – reference: I.-J. Huang, A.M. Despain, Generating instruction sets and microarchitectures from applications, in: Proceedings of International Conference on Computer Aided Design (ICCAD-94), November 1994, pp. 391–396 – reference: AF-TM-0056.000, ATM Traffic Specification Version 4.0, ATM Forum, April 1996 – reference: L. Thiele, S. Chakraborty, M. Gries, S. Künzli, Design space exploration of network processor architectures, in: Proceedings of 8th International Symposium on High-Performance Computer Architecture; Workshop on Network Processors, Cambridge, MA, February 3, 2002 – reference: J. van Lunteren, A.P.J. Engbersen, Dynamic multi-field packet classification, in: Proceedings of IEEE Globecom, November 2002 – reference: RFC 3031, Multiprotocol Label Switching, E. Rosen et al., January 2001 – reference: RFC 2309, Recommendations on Queue Management and Congestion Avoidance in the Internet, B. Braden et al., April 1998 – reference: SystemC, Version 2.0 Beta-1, User’s Guide, 2001 – volume: 41 start-page: 641 year: 2003 end-page: 665 ident: BIB8 article-title: Fast and accurate performance evaluation of network processor architectures: combining simulation with analytical estimation publication-title: Computer Networks – start-page: 149 year: 2002 end-page: 164 ident: BIB33 article-title: Design tradeoffs for embedded network processors publication-title: ARCS 2002 – reference: M. Arnold, H. Corporaal, Designing domain-specific processors, in: Proceedings of 9th International Symposium on Hardware/Software Codesign (CODES’01), April 2001, pp. 61–66 – year: 1986 ident: BIB4 article-title: Compilers – volume: 1 start-page: 397 year: 1993 end-page: 413 ident: BIB14 article-title: Random early detection gateways for congestion avoidance publication-title: ACM Transactions on Networking – reference: P.N. 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Fettweis, A generic tool set for application specific processor architectures, in: Proceedings of 8th International Workshop on Hardware/Software Codesign (CODES 2000), May 2000, pp. 126–130 – reference: Agere Systems, Inc., The Challenge for Next Generation Network Processors, White Paper, April 2001 – reference: S. Pees, A. Hoffmann, V. Zivojnovic, H. Meyr, LISA: Machine description language for cycle-accurate models of programmable dsp architectures, in: Proceedings of 35th Design Automation Conference (DAC’99), June 1999, pp. 933–938 – reference: M. Adiletta, M. Rosenbluth, D. Bernstein, G. Wolrich, H. Wilkinson, The next generation of Intel IXP network processors, Intel Technology Journal, vol. 06(03), August 15, 2002 – reference: IBM Corporation, Network Processor 4GS3 Overview, Application Note, October 1999 – reference: RFC 1633, Integrated Services in the Internet Architecture: An Overview, R. Braden, D. Clark, S. Shenker, July 1994 – ident: 10.1016/S1389-1286(02)00453-X_BIB9 – ident: 10.1016/S1389-1286(02)00453-X_BIB11 – ident: 10.1016/S1389-1286(02)00453-X_BIB26 doi: 10.17487/rfc1633 – ident: 10.1016/S1389-1286(02)00453-X_BIB13 – volume: 30 start-page: 79 issue: 9 year: 1997 ident: 10.1016/S1389-1286(02)00453-X_BIB17 article-title: A single-chip multiprocessor publication-title: IEEE Computer doi: 10.1109/2.612253 – year: 1986 ident: 10.1016/S1389-1286(02)00453-X_BIB4 – ident: 10.1016/S1389-1286(02)00453-X_BIB25 doi: 10.1145/309847.310101 – volume: 1 start-page: 397 issue: 4 year: 1993 ident: 10.1016/S1389-1286(02)00453-X_BIB14 article-title: Random early detection gateways for congestion avoidance publication-title: ACM Transactions on Networking doi: 10.1109/90.251892 – ident: 10.1016/S1389-1286(02)00453-X_BIB29 doi: 10.17487/rfc3031 – year: 1994 ident: 10.1016/S1389-1286(02)00453-X_BIB15 – ident: 10.1016/S1389-1286(02)00453-X_BIB19 – ident: 10.1016/S1389-1286(02)00453-X_BIB21 – ident: 10.1016/S1389-1286(02)00453-X_BIB23 doi: 10.1109/GLOCOM.2002.1189025 – ident: 10.1016/S1389-1286(02)00453-X_BIB30 – ident: 10.1016/S1389-1286(02)00453-X_BIB2 – ident: 10.1016/S1389-1286(02)00453-X_BIB12 doi: 10.1145/334012.334036 – volume: 41 start-page: 641 issue: 5 year: 2003 ident: 10.1016/S1389-1286(02)00453-X_BIB8 article-title: Fast and accurate performance evaluation of network processor architectures: combining simulation with analytical estimation publication-title: Computer Networks doi: 10.1016/S1389-1286(02)00454-1 – ident: 10.1016/S1389-1286(02)00453-X_BIB10 – ident: 10.1016/S1389-1286(02)00453-X_BIB6 – ident: 10.1016/S1389-1286(02)00453-X_BIB31 – ident: 10.1016/S1389-1286(02)00453-X_BIB5 doi: 10.1145/371636.371677 – ident: 10.1016/S1389-1286(02)00453-X_BIB7 doi: 10.1109/IZSBC.2002.991753 – ident: 10.1016/S1389-1286(02)00453-X_BIB27 doi: 10.17487/rfc2309 – ident: 10.1016/S1389-1286(02)00453-X_BIB28 doi: 10.17487/rfc2475 – ident: 10.1016/S1389-1286(02)00453-X_BIB32 doi: 10.1016/B978-155860875-7.50022-3 – ident: 10.1016/S1389-1286(02)00453-X_BIB20 – ident: 10.1016/S1389-1286(02)00453-X_BIB24 – ident: 10.1016/S1389-1286(02)00453-X_BIB18 – ident: 10.1016/S1389-1286(02)00453-X_BIB16 – start-page: 149 year: 2002 ident: 10.1016/S1389-1286(02)00453-X_BIB33 article-title: Design tradeoffs for embedded network processors – ident: 10.1016/S1389-1286(02)00453-X_BIB3 – ident: 10.1016/S1389-1286(02)00453-X_BIB22 doi: 10.1109/GLOCOM.2001.965853 – ident: 10.1016/S1389-1286(02)00453-X_BIB1
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Snippet	We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor... A design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores,... Article included in a special issue devoted to the theme: Network processors. Presents a design methodology for a modular network processor architecture that...
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Title	Design methodology for a modular service-driven network processor architecture
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