High throughput and area-efficient FPGA implementation of AES for high-traffic applications

This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal o...

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Vydáno v:	Chronic diseases and translational medicine Ročník 14; číslo 6; s. 344 - 352
Hlavní autoři:	Shahbazi, Karim, Ko, Seok-Bum
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Beijing The Institution of Engineering and Technology 01.11.2020 John Wiley & Sons, Inc
Témata:	add‐round‐key advanced encryption standard‐128 AES‐128 Algorithms area‐efficient FPGA implementation Critical path Cryptography Data encryption data throughput Design Digital video recorders Field programmable gate arrays FPGA efficiency cryptosystem frequency 622.4 MHz high throughput field‐programmable gate array high‐traffic applications Internet logic design new‐affine‐transformation pipelining techniques Research Article shift‐rows Software symmetric key encryption algorithm telecommunication traffic VHDL Xilinx Virtex‐5 FPGA efficiency cryptosystem AES-128 field programmable gate arrays area-efficient FPGA implementation high-traffic applications shift-rows cryptography frequency 622.4 MHz Xilinx Virtex-5 pipelining techniques high throughput field-programmable gate array VHDL new-affine-transformation data throughput advanced encryption standard-128 symmetric key encryption algorithm logic design telecommunication traffic add-round-key
ISSN:	1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
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