High throughput and area-efficient FPGA implementation of AES for high-traffic applications

This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal o...

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Vydáno v:	Chronic diseases and translational medicine Ročník 14; číslo 6; s. 344 - 352
Hlavní autoři:	Shahbazi, Karim, Ko, Seok-Bum
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Beijing The Institution of Engineering and Technology 01.11.2020 John Wiley & Sons, Inc
Témata:	add‐round‐key advanced encryption standard‐128 AES‐128 Algorithms area‐efficient FPGA implementation Critical path Cryptography Data encryption data throughput Design Digital video recorders Field programmable gate arrays FPGA efficiency cryptosystem frequency 622.4 MHz high throughput field‐programmable gate array high‐traffic applications Internet logic design new‐affine‐transformation pipelining techniques Research Article shift‐rows Software symmetric key encryption algorithm telecommunication traffic VHDL Xilinx Virtex‐5 FPGA efficiency cryptosystem AES-128 field programmable gate arrays area-efficient FPGA implementation high-traffic applications shift-rows cryptography frequency 622.4 MHz Xilinx Virtex-5 pipelining techniques high throughput field-programmable gate array VHDL new-affine-transformation data throughput advanced encryption standard-128 symmetric key encryption algorithm logic design telecommunication traffic add-round-key
ISSN:	1751-8601, 1751-861X, 2095-882X, 1751-861X, 2589-0514
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Shrnutí:	This study presents a high throughput field-programmable gate array (FPGA) implementation of advanced encryption standard-128 (AES-128). AES is a well-known symmetric key encryption algorithm with high security against different attacks that are widely used in different applications. The main goal of this study is to design a high throughput and FPGA efficiency (FPGA-Eff) cryptosystem for high-traffic applications. To achieve high throughput, loop-unrolling, inner and outer pipelining techniques are employed. In AES, substitution bytes (Sub-Bytes) is one of the costly functions that occupy a large number of resources and has a large delay. To reduce the area of Sub-Bytes, new-affine-transformation, which is the combination of inverse isomorphic and affine transformation, is proposed and employed. Besides that, AES has been modified according to the proposed architecture. For the first nine rounds, Shift-Rows and Sub-Bytes have been exchanged, and Shift-Rows is merged with Add-Round-Key. To make an equal latency between stages, Mix-Columns is divided into two different stages. AES is implemented in counter mode on Xilinx Virtex-5 using VHDL. The proposed implementation achieves a throughput of 79.7 Gbps, FPGA-Eff of 13.3 Mbps/slice, and frequency of 622.4 MHz. Compared to the state-of-the-art work, the proposed design has improved data throughput by 8.02% and FPGA-Eff by 22.63%.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1751-8601 1751-861X 2095-882X 1751-861X 2589-0514
DOI:	10.1049/iet-cdt.2019.0179