A hardware-oriented gold-washing adaptive vector quantizer and its VLSI architectures for image data compression
The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for...
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| Veröffentlicht in: | IEEE transactions on circuits and systems for video technology Jg. 10; H. 8; S. 1502 - 1513 |
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IEEE
01.12.2000
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| Abstract | The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N+N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k+1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10/sup 6/ samples/s), respectively. These results are good enough for most of the practical image compression systems. |
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| AbstractList | The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k 1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10(6) samples/s), respectively. These results are good enough for most of the practical image compression systems The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N+N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k+1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10 super(6) samples/s), respectively. These results are good enough for most of the practical image compression systems The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. In this paper, we propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N + N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k + 1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10 super(6) samples/s), respectively. These results are good enough for most of the practical image compression systems. The gold-washing (GW) mechanism is an efficient on-line codebook refining technique for adaptive vector quantization (AVQ). However, the mechanism is essentially not suitable for hardware implementation. We propose a hardware-oriented GW-AVQ scheme based on the least-recently-used (LRU) strategy for codevector selection and the block-data-interpolation (BDI) algorithm for vector generation. We also present the VLSI architectures for the key components of GW-AVQ, including a 2-D systolic array (SABVQ) and a 1-D linear array (LABVQ) for full-search VQ, a pipeline BDI encoder (PBDI-E) and decoder (PBDI-D), and the LRU strategy. The SABVQ architecture can perform in O(k) time with O(N+N/k) area and O(k) I/O complexity; the LABVQ architecture reaches O(N) time, O(k+1) area, and O(k) I/O complexity, where k and N are the codevector dimension and codebook size, respectively. The PBDI architecture reaches O(1) time, O(k) area, and O(1) I/O complexity. The LRU architecture can perform in O(1) time, O(N) area and O(1) I/O complexity. With VHDL implementation, the maximum computational capacity of SABVQ, LABVQ, five-stage PBDI-E, PBDI-D, and LRU are 45, 2.8, 1667, 2232, and 246 (10/sup 6/ samples/s), respectively. These results are good enough for most of the practical image compression systems. |
| Author | Shaou-Gang Miaou Wen-Song Chung |
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| Keywords | VLSI circuit Vector quantization Image processing Pipelines Data compression Image databank Gold coating Decoding circuit Encoding Experimental study Adaptive method Implementation Algorithms Computer hardware Linear antennas Strategy Quantifier Systolic arrays |
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| Title | A hardware-oriented gold-washing adaptive vector quantizer and its VLSI architectures for image data compression |
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