The AXIOM software layers
•AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).•The Software Layers developed at the AXIOM project are explained.•OmpSs provides an easy way to execute heterogeneous codes in multiple cores. People and objects will soon share the same digital network for information exc...
Saved in:
| Published in: | Microprocessors and microsystems Vol. 47; pp. 262 - 277 |
|---|---|
| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , |
| Format: | Journal Article Publication |
| Language: | English |
| Published: |
Elsevier B.V
01.11.2016
|
| Subjects: | |
| ISSN: | 0141-9331, 1872-9436 |
| Online Access: | Get full text |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Abstract | •AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).•The Software Layers developed at the AXIOM project are explained.•OmpSs provides an easy way to execute heterogeneous codes in multiple cores.
People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed.
The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics). |
|---|---|
| AbstractList | •AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).•The Software Layers developed at the AXIOM project are explained.•OmpSs provides an easy way to execute heterogeneous codes in multiple cores.
People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed.
The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics). AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).The Software Layers developed at the AXIOM project are explained.OmpSs provides an easy way to execute heterogeneous codes in multiple cores. People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed.The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics). Peer Reviewed |
| Author | Bueno, Javier Segura, Carlos Navarro, Nacho Oro, David Martorell, Xavier Cherkashin, Artem Scordino, Claudio Rizzo, Antonio Vidal, Miquel Hernando, Javier Gai, Paolo Ayguadé, Eduard Pnevmatikatos, Dionisios N. Catani, Davide Bosch, Jaume Theodoropoulos, Dimitris Rodríguez, Javier Bettin, Nicola Fernández, Carles Passera, Pierluigi Giorgi, Roberto Pomella, Alberto Filgueras, Antonio Álvarez, Carlos Jiménez-González, Daniel |
| Author_xml | – sequence: 1 givenname: Carlos orcidid: 0000-0003-0536-5183 surname: Álvarez fullname: Álvarez, Carlos email: carlos.alvarez@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 2 givenname: Eduard surname: Ayguadé fullname: Ayguadé, Eduard email: eduard.ayguade@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 3 givenname: Jaume surname: Bosch fullname: Bosch, Jaume email: jaume.bosch@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 4 givenname: Javier surname: Bueno fullname: Bueno, Javier email: javier.bueno@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 5 givenname: Artem orcidid: 0000-0002-7020-029X surname: Cherkashin fullname: Cherkashin, Artem email: artem.cherkashin@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 6 givenname: Antonio surname: Filgueras fullname: Filgueras, Antonio email: antonio.filgueras@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 7 givenname: Daniel surname: Jiménez-González fullname: Jiménez-González, Daniel email: daniel.jimenez@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 8 givenname: Xavier surname: Martorell fullname: Martorell, Xavier email: xavier.martorell@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 9 givenname: Nacho surname: Navarro fullname: Navarro, Nacho email: nacho.navarro@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 10 givenname: Miquel orcidid: 0000-0002-1973-8289 surname: Vidal fullname: Vidal, Miquel email: miquel.vidal@bsc.es organization: Barcelona Supercomputing Center and Computer Architecture Dept., Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 11 givenname: Dimitris orcidid: 0000-0002-0707-9415 surname: Theodoropoulos fullname: Theodoropoulos, Dimitris email: dtheodor@ics.forth.gr organization: FORTH-ICS, Greece – sequence: 12 givenname: Dionisios N. surname: Pnevmatikatos fullname: Pnevmatikatos, Dionisios N. email: pnevmati@ics.forth.gr organization: FORTH-ICS, Greece – sequence: 13 givenname: Davide surname: Catani fullname: Catani, Davide email: davide.catani@seco.com organization: SECO, Arezzo, Italy – sequence: 14 givenname: David surname: Oro fullname: Oro, David email: david.oro@hertasecurity.com organization: Herta Security, Barcelona, Spain – sequence: 15 givenname: Carles surname: Fernández fullname: Fernández, Carles email: carles.fernandez@hertasecurity.com organization: Herta Security, Barcelona, Spain – sequence: 16 givenname: Carlos surname: Segura fullname: Segura, Carlos email: cseguramail@gmail.com organization: Herta Security, Barcelona, Spain – sequence: 17 givenname: Javier surname: Rodríguez fullname: Rodríguez, Javier email: javier.rodriguez@hertasecurity.com organization: Herta Security, Barcelona, Spain – sequence: 18 givenname: Javier orcidid: 0000-0002-1730-8154 surname: Hernando fullname: Hernando, Javier email: javier.hernando@upc.edu organization: Universitat Politecnica de Catalunya, Barcelona, Spain – sequence: 19 givenname: Claudio surname: Scordino fullname: Scordino, Claudio email: claudio@evidence.eu.com organization: Evidence Srl, Pisa, Italy – sequence: 20 givenname: Paolo surname: Gai fullname: Gai, Paolo email: pj@evidence.eu.com organization: Evidence Srl, Pisa, Italy – sequence: 21 givenname: Pierluigi surname: Passera fullname: Passera, Pierluigi email: pierluigi.passera@vimar.com organization: VIMAR SpA, Marostica, Italy – sequence: 22 givenname: Alberto surname: Pomella fullname: Pomella, Alberto email: alberto.pomella@vimar.com organization: VIMAR SpA, Marostica, Italy – sequence: 23 givenname: Nicola orcidid: 0000-0002-3142-1911 surname: Bettin fullname: Bettin, Nicola email: nicola.bettin@vimar.com organization: VIMAR SpA, Marostica, Italy – sequence: 24 givenname: Antonio surname: Rizzo fullname: Rizzo, Antonio email: antonioriz@gmail.com organization: University of Siena, Siena, Italy – sequence: 25 givenname: Roberto orcidid: 0000-0003-0384-8229 surname: Giorgi fullname: Giorgi, Roberto email: giorgi@dii.unisi.it organization: University of Siena, Siena, Italy |
| BookMark | eNqFkMFKAzEQhoNUsK0-gOChL7DrTJJNuh6EUqwWKr304C2k2VlMaXdLsip9e1NaEDzoYWb4D9_P8A1Yr2kbYuwOIUdAdb_Jd97tQ5vzlHLQOQC_YH0ca56VUqge6wNKzEoh8IoNYtwAQAGK99nt6p1Gk7f58nUU27r7soFGW3ugEK_ZZW23kW7Od8hWs6fV9CVbLJ_n08kic6KUXYYktasFrgsNzoKypRWkNWiHSpW1KKjkhJWWXDurihpLux5XNRZpE2gxZHiqdfHDmUCOgrOdaa3_CcfhoLnhmstCJEaemdDGGKg2--B3NhwMgjkaMRtzMmKORgxok4wk7OEX5nxnO982XbB--x_8eIIpufj0FEx0nhpHlU9_dqZq_d8F32b2fxo |
| CitedBy_id | crossref_primary_10_1016_j_matpr_2021_04_639 crossref_primary_10_1109_ACCESS_2023_3288431 crossref_primary_10_1109_MDAT_2019_2952335 crossref_primary_10_1016_j_micpro_2018_08_005 |
| Cites_doi | 10.1016/j.micpro.2014.04.001 10.1109/TPDS.2013.125 10.1016/j.patrec.2015.06.006 10.1145/1837853.1693502 10.2172/862127 10.1177/1094342007078442 10.1145/1103845.1094852 10.1177/1094342009106195 |
| ContentType | Journal Article Publication |
| Contributor | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions Universitat Politècnica de Catalunya. VEU - Grup de Tractament de la Parla Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors Facultat d'Informàtica de Barcelona Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions |
| Contributor_xml | – sequence: 1 fullname: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors – sequence: 2 fullname: Facultat d'Informàtica de Barcelona – sequence: 3 fullname: Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions – sequence: 4 fullname: Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions – sequence: 5 fullname: Universitat Politècnica de Catalunya. VEU - Grup de Tractament de la Parla |
| Copyright | 2016 The Authors info:eu-repo/semantics/openAccess http://creativecommons.org/licenses/by-nc-nd/3.0/es |
| Copyright_xml | – notice: 2016 The Authors – notice: info:eu-repo/semantics/openAccess <a href="http://creativecommons.org/licenses/by-nc-nd/3.0/es/">http://creativecommons.org/licenses/by-nc-nd/3.0/es/</a> |
| DBID | 6I. AAFTH AAYXX CITATION XX2 |
| DOI | 10.1016/j.micpro.2016.07.002 |
| DatabaseName | ScienceDirect Open Access Titles Elsevier:ScienceDirect:Open Access CrossRef Recercat |
| DatabaseTitle | CrossRef |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISSN | 1872-9436 |
| EndPage | 277 |
| ExternalDocumentID | oai_recercat_cat_2072_272453 10_1016_j_micpro_2016_07_002 S0141933116300850 |
| GroupedDBID | --K --M -~X .DC .~1 0R~ 123 1B1 1~. 1~5 29M 4.4 457 4G. 5VS 6I. 7-5 71M 8P~ 9JN AACTN AAEDT AAEDW AAFTH AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAXUO AAYFN ABBOA ABJNI ABMAC ABXDB ABYKQ ACDAQ ACGFS ACIWK ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADMUD ADTZH AEBSH AECPX AEKER AENEX AFKWA AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD AXJTR BJAXD BKOJK BLXMC CS3 DU5 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 F5P FDB FEDTE FGOYB FIRID FNPLU FYGXN G-2 G-Q G8K GBLVA GBOLZ HLZ HVGLF HZ~ IHE J1W JJJVA KOM LG9 LY7 M41 MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. PQQKQ Q38 RIG ROL RPZ SBC SDF SDG SDP SES SET SEW SPC SPCBC SST SSV SSZ T5K T9H TN5 UHS WUQ XOL XPP ZMT ~G- 9DU AATTM AAXKI AAYWO AAYXX ABDPE ABWVN ACLOT ACRPL ACVFH ADCNI ADNMO AEIPS AEUPX AFJKZ AFPUW AIGII AIIUN AKBMS AKRWK AKYEP ANKPU APXCP CITATION EFKBS ~HD XX2 |
| ID | FETCH-LOGICAL-c394t-1e47cf31b570ca06a9a3e7707c1669f35e92e1d7427ca65f19ab8df15b8de073 |
| ISICitedReferencesCount | 10 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000390513300003&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 0141-9331 |
| IngestDate | Fri Nov 07 13:38:02 EST 2025 Sat Nov 29 05:51:32 EST 2025 Tue Nov 18 21:45:49 EST 2025 Fri Feb 23 02:26:34 EST 2024 |
| IsDoiOpenAccess | true |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Keywords | Smart video-surveillance Smart home Cyber-physical systems FPGA Programming Distributed shared memory Ompss Cluster programming |
| Language | English |
| License | This is an open access article under the CC BY-NC-ND license. |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-c394t-1e47cf31b570ca06a9a3e7707c1669f35e92e1d7427ca65f19ab8df15b8de073 |
| ORCID | 0000-0002-3142-1911 0000-0003-0536-5183 0000-0002-1973-8289 0000-0002-0707-9415 0000-0003-0384-8229 0000-0002-1730-8154 0000-0002-7020-029X |
| OpenAccessLink | https://recercat.cat/handle/2072/272453 |
| PageCount | 16 |
| ParticipantIDs | csuc_recercat_oai_recercat_cat_2072_272453 crossref_primary_10_1016_j_micpro_2016_07_002 crossref_citationtrail_10_1016_j_micpro_2016_07_002 elsevier_sciencedirect_doi_10_1016_j_micpro_2016_07_002 |
| PublicationCentury | 2000 |
| PublicationDate | November 2016 2016-11-00 2016-11-01 |
| PublicationDateYYYYMMDD | 2016-11-01 |
| PublicationDate_xml | – month: 11 year: 2016 text: November 2016 |
| PublicationDecade | 2010 |
| PublicationTitle | Microprocessors and microsystems |
| PublicationYear | 2016 |
| Publisher | Elsevier B.V |
| Publisher_xml | – name: Elsevier B.V |
| References | Huerta, Fernández, Segura, Hernando, Prati (bib0048) 2015; 68 Giorgi (bib0020) 2015 Bueno, Martinell, Durán, Farreras, Martorell, Badía, Ayguadé, Labarta (bib0032) 2011 Weis (bib0023) 2014 Verdoscia, Vaccaro, Giorgi (bib0017) 2015 Hess, Jost, Müller, Rühle (bib0041) 2002 Parade Giorgi, Faraboschi (bib0010) 2014 Filgueras, Gil, Álvarez, Jiménez-González, Martorell, Langer, Noguera (bib0025) 2013 Giorgi (bib0009) 2014; 38 Taigman, Yang, Ranzato, Wolf (bib0047) 2014 Canis, Choi, Aldham, Zhang, Kammoona, Anderson, Brown, Czajkowski (bib0028) 2011 Giorgi (bib0007) 2012 Charles, Grothoff, Saraswat, Donawa, Kielstra, Ebcioglu, von Praun, Sarkar (bib0034) 2005; 40 Khronos OpenCL Working Group, The OpenCL Specification, version 1.2, 2011. URL https://www.khronos.org/registry/cl/specs/opencl-1.2.pdf Kaxiras, Klaftenegger, Norgren, Ros, Sagonas (bib0038) 2015 Ho, Mondelli, Scionti, Solinas, Portero, Giorgi (bib0008) 2015 PGI Accelerator Programming Model for Fortran & C, The Portland Group, 2010. Verdoscia, Vaccaro, Giorgi (bib0016) 2014 R. Ferrer, S. Royuela, D. Caballero, A. Durán, X. Martorell, E. Ayguadé, Mercurium: design decisions for a s2s compiler, Cetus Users and Compiler Infastructure Workshop in conjunction with PACT 2011, 2011. . S. Chetlur, C. Woolley, P. Vandermersch, J. Cohen, J. Tran, B. Catanzaro, E. Shelhamer, cuDNN: efficient primitives for deep learning, arXiv preprint arXiv:1410.0759, 2014. URL http://arxiv.org/abs/1410.0759 Planas, Badía, Ayguadé, Labarta (bib0014) 2009; 23 Filgueras, Gil, Jiménez-González, Álvarez, Martorell, Langer, Noguera, Vissers (bib0024) 2014 Giorgi, Scionti (bib0006) 2015 Yazdanpanah, Álvarez-Martínez, Jiménez-González, Etsion (bib0015) 2014; 25 Scionti, Kavvadias, Giorgi (bib0013) 2014 Dolbeau, Bihan, Bodin (bib0031) 2007 Ayguadé, Badía, Cabrera, Durán, González, Igual, Jiménez, Labarta, Martorell, Mayo, Pérez, Quintana-Orti (bib0003) 2009; 5568 Ho, Portero, Solinas, Scionti, Mondelli, Faraboschi, Giorgi (bib0019) 2014 Marjanovic, Labarta, Ayguadé, Valero (bib0036) 2010; 45 Giorgi (bib0021) 2015; 14 UPC Consortium, UPC Language Specifications v1.2, Report Number: LBNL-59208, 2005. Chamberlain, Callahan, Zima (bib0035) 2007; 21 Altera, Corp., Nios II C2H Compiler User Guide, 2009. URL: www.altera.com Kee, Kim, Ha (bib0045) 2003 Weis, Garbade, Wolf, Fechner, Mendelson, Giorgi, Ungerer (bib0022) 2011 Villarreal, Park, Najjar, Halstead (bib0026) 2010 Costa, Cortes, Martorell, Ayguadé, Labarta (bib0046) 2006; 6 Solinas (bib0018) 2013 Jiajia Burresi, Giorgi (bib0011) 2015 Omni/scash The jump software dsm system V. Pillet, J. Labarta, T. Cortes, S. Girona, PARAVER: a Tool to Visualize and Analyze Parallel Code Technical Report UPC-CEPBA-95-03, European Center for Parallelism of Barcelona (CEPBA), Universitat Politècnica de Catalunya (UPC), 1995. Angelova, Krizhevsky, Vanhoucke, Ogale, Ferguson (bib0049) 2015 Goransson, Ruiz (bib0001) 2013 Cheung, Hwang (bib0043) 2000 Najjar, Villarreal (bib0027) 2013 Jia, Shelhamer, Donahue, Karayev, Long, Girshick, Guadarrama, Darrell (bib0050) 2014 Monk (bib0002) 2013 Puzovic, McKee, Eres, Zaks, Gai, S., Giorgi (bib0012) 2010 Chamberlain (10.1016/j.micpro.2016.07.002_bib0035) 2007; 21 Jia (10.1016/j.micpro.2016.07.002_bib0050) 2014 10.1016/j.micpro.2016.07.002_bib0030 Planas (10.1016/j.micpro.2016.07.002_bib0014) 2009; 23 10.1016/j.micpro.2016.07.002_bib0037 Filgueras (10.1016/j.micpro.2016.07.002_bib0024) 2014 Najjar (10.1016/j.micpro.2016.07.002_bib0027) 2013 10.1016/j.micpro.2016.07.002_bib0033 Kaxiras (10.1016/j.micpro.2016.07.002_bib0038) 2015 Verdoscia (10.1016/j.micpro.2016.07.002_bib0016) 2014 10.1016/j.micpro.2016.07.002_bib0039 Ho (10.1016/j.micpro.2016.07.002_bib0008) 2015 Cheung (10.1016/j.micpro.2016.07.002_bib0043) 2000 10.1016/j.micpro.2016.07.002_bib0040 Giorgi (10.1016/j.micpro.2016.07.002_bib0007) 2012 Dolbeau (10.1016/j.micpro.2016.07.002_bib0031) 2007 Charles (10.1016/j.micpro.2016.07.002_bib0034) 2005; 40 10.1016/j.micpro.2016.07.002_bib0004 Taigman (10.1016/j.micpro.2016.07.002_bib0047) 2014 10.1016/j.micpro.2016.07.002_bib0005 10.1016/j.micpro.2016.07.002_bib0042 Giorgi (10.1016/j.micpro.2016.07.002_bib0021) 2015; 14 Monk (10.1016/j.micpro.2016.07.002_bib0002) 2013 10.1016/j.micpro.2016.07.002_bib0044 Solinas (10.1016/j.micpro.2016.07.002_bib0018) 2013 Huerta (10.1016/j.micpro.2016.07.002_bib0048) 2015; 68 Scionti (10.1016/j.micpro.2016.07.002_bib0013) 2014 Burresi (10.1016/j.micpro.2016.07.002_bib0011) 2015 Yazdanpanah (10.1016/j.micpro.2016.07.002_bib0015) 2014; 25 Verdoscia (10.1016/j.micpro.2016.07.002_bib0017) 2015 Marjanovic (10.1016/j.micpro.2016.07.002_bib0036) 2010; 45 Giorgi (10.1016/j.micpro.2016.07.002_bib0020) 2015 Weis (10.1016/j.micpro.2016.07.002_bib0023) 2014 Goransson (10.1016/j.micpro.2016.07.002_bib0001) 2013 10.1016/j.micpro.2016.07.002_bib0051 Hess (10.1016/j.micpro.2016.07.002_bib0041) 2002 Giorgi (10.1016/j.micpro.2016.07.002_bib0009) 2014; 38 Bueno (10.1016/j.micpro.2016.07.002_bib0032) 2011 Giorgi (10.1016/j.micpro.2016.07.002_bib0006) 2015 Kee (10.1016/j.micpro.2016.07.002_bib0045) 2003 Puzovic (10.1016/j.micpro.2016.07.002_bib0012) 2010 Weis (10.1016/j.micpro.2016.07.002_bib0022) 2011 Ayguadé (10.1016/j.micpro.2016.07.002_bib0003) 2009; 5568 Angelova (10.1016/j.micpro.2016.07.002_bib0049) 2015 Villarreal (10.1016/j.micpro.2016.07.002_bib0026) 2010 Ho (10.1016/j.micpro.2016.07.002_bib0019) 2014 10.1016/j.micpro.2016.07.002_bib0029 Filgueras (10.1016/j.micpro.2016.07.002_bib0025) 2013 Giorgi (10.1016/j.micpro.2016.07.002_bib0010) 2014 Costa (10.1016/j.micpro.2016.07.002_bib0046) 2006; 6 Canis (10.1016/j.micpro.2016.07.002_bib0028) 2011 |
| References_xml | – reference: R. Ferrer, S. Royuela, D. Caballero, A. Durán, X. Martorell, E. Ayguadé, Mercurium: design decisions for a s2s compiler, Cetus Users and Compiler Infastructure Workshop in conjunction with PACT 2011, 2011. – volume: 40 start-page: 519 year: 2005 end-page: 538 ident: bib0034 article-title: X10: an object-oriented approach to non-uniform cluster computing publication-title: SIGPLAN Not. – reference: The jump software dsm system, – start-page: 38 year: 2011 end-page: 44 ident: bib0022 article-title: A fault detection and recovery architecture for a teradevice dataflow system publication-title: IEEE DFM) – start-page: 33 year: 2011 end-page: 36 ident: bib0028 article-title: Legup: High-level synthesis for fpga-based processor/accelerator systems publication-title: Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays – start-page: 272 year: 2013 end-page: 279 ident: bib0018 article-title: The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices publication-title: DSD – year: 2003 ident: bib0045 article-title: ParADE: an OpenMP Programming Environment for SMP Cluster Systems publication-title: Supercomputing 2003 (SC’03) – start-page: 303 year: 2012 end-page: 304 ident: bib0007 article-title: iTERAFLUX: exploiting dataflow parallelism in teradevices publication-title: ACM Computing Frontiers – reference: Parade, – reference: V. Pillet, J. Labarta, T. Cortes, S. Girona, PARAVER: a Tool to Visualize and Analyze Parallel Code Technical Report UPC-CEPBA-95-03, European Center for Parallelism of Barcelona (CEPBA), Universitat Politècnica de Catalunya (UPC), 1995. – start-page: 1 year: 2015 end-page: 6 ident: bib0011 article-title: A field experience for a vehicle recognition system using magnetic sensors publication-title: IEEE MECO – start-page: 1 year: 2015 end-page: 6 ident: bib0017 article-title: A matrix multiplier case study for an evaluation of a configurable dataflow-machine publication-title: ACM CF’15 - LP-EMS – year: 2015 ident: bib0049 article-title: Real-time pedestrian detection with deep network cascades publication-title: Proceedings of BMVC 2015 – start-page: 675 year: 2014 end-page: 678 ident: bib0050 article-title: Caffe: convolutional architecture for fast feature embedding publication-title: Proceedings of the ACM International Conference on Multimedia – year: 2013 ident: bib0002 publication-title: Programming Arduino Next Steps: Going Further with Sketches – reference: Khronos OpenCL Working Group, The OpenCL Specification, version 1.2, 2011. URL https://www.khronos.org/registry/cl/specs/opencl-1.2.pdf – start-page: 290 year: 2013 end-page: 291 ident: bib0025 article-title: Heterogeneous tasking on smp/fpga socs: The case of ompss and the zynq publication-title: 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) – reference: S. Chetlur, C. Woolley, P. Vandermersch, J. Cohen, J. Tran, B. Catanzaro, E. Shelhamer, cuDNN: efficient primitives for deep learning, arXiv preprint arXiv:1410.0759, 2014. URL http://arxiv.org/abs/1410.0759 – reference: Jiajia, – volume: 38 start-page: 976 year: 2014 end-page: 990 ident: bib0009 article-title: TERAFLUX: harnessing dataflow in next generation teradevices publication-title: Microprocess. Microsyst. – volume: 21 start-page: 291 year: 2007 end-page: 312 ident: bib0035 article-title: Parallel programmability and the chapel language publication-title: Int. J. High Perform. Comput. Appl. – volume: 14 start-page: 794 year: 2015 end-page: 805 ident: bib0021 article-title: Transactional memory on a dataflow architecture for accelerating haskell publication-title: WSEAS Trans. Comput. – year: 2000 ident: bib0043 article-title: Jump-dp: A software dsm system with low-latency communication support publication-title: PDPTA – start-page: 1 year: 2015 end-page: 2 ident: bib0008 article-title: Enhancing an x86_64 multi-core architecture with data-flow execution support publication-title: ACM Proc. of Computing Frontiers – volume: 25 start-page: 1489 year: 2014 end-page: 1509 ident: bib0015 article-title: Hybrid dataflow/von-neumann architectures publication-title: IEEE Trans. Parallel Distrib. Syst. – start-page: 60 year: 2014 end-page: 65 ident: bib0010 article-title: An introduction to df-threads and their execution model publication-title: IEEE MPP – volume: 68 start-page: 239 year: 2015 end-page: 249 ident: bib0048 article-title: A deep analysis on age estimation publication-title: Pattern Recognit. Lett. – start-page: 62 year: 2014 end-page: 65 ident: bib0013 article-title: Dynamic power reduction in self-adaptive embedded systems through benchmark analysis publication-title: IEEE MECO – reference: UPC Consortium, UPC Language Specifications v1.2, Report Number: LBNL-59208, 2005. – start-page: 1701 year: 2014 end-page: 1708 ident: bib0047 article-title: Deepface: Closing the gap to human-level performance in face verification publication-title: IEEE Conference on Computer Vision and Pattern Recognition – start-page: 1 year: 2015 end-page: 10 ident: bib0006 article-title: A scalable thread scheduling co-processor based on data-flow principles publication-title: ELSEVIER Future Gener. Comput. Syst. – start-page: 555 year: 2011 end-page: 566 ident: bib0032 article-title: Productive cluster programming with ompss publication-title: Proceedings of the 17th International Conference on Parallel Processing - Volume Part I, Euro-Par’11 – start-page: 3 year: 2015 end-page: 14 ident: bib0038 article-title: Turning centralized coherence and distributed critical-section execution on their head: A new approach for scalable distributed shared memory publication-title: Proc. of HPDC – reference: PGI Accelerator Programming Model for Fortran & C, The Portland Group, 2010. – start-page: 30 year: 2014 end-page: 37 ident: bib0016 article-title: A clockless computing system based on the static dataflow paradigm publication-title: Proc. IEEE Int.l Workshop on Data-Flow Execution Models for Extreme Scale Computing (DFM-2014) – start-page: 1 year: 2010 end-page: 4 ident: bib0012 article-title: A multi-pronged approach to benchmark characterization publication-title: IEEE CLUSTER – start-page: 1 year: 2014 end-page: 25 ident: bib0023 article-title: Architectural support for fault tolerance in a teradevice dataflow system publication-title: Springer Int’l J. Parallel Program. – volume: 23 start-page: 284 year: 2009 end-page: 299 ident: bib0014 article-title: Hierarchical task-based programming with StarSs publication-title: Int. J. High Perform. Comput. Appl. – reference: Altera, Corp., Nios II C2H Compiler User Guide, 2009. URL: www.altera.com – start-page: 127 year: 2010 end-page: 134 ident: bib0026 article-title: Designing modular hardware accelerators in c with roccc 2.0. publication-title: FCCM – year: 2013 ident: bib0001 publication-title: Professional Android Open Accessory Programming with Arduino – reference: Omni/scash – volume: 6 start-page: 647—658 year: 2006 ident: bib0046 article-title: Paper running openmp applications efficiently on an everything-shared sdsm publication-title: (JPDC) – start-page: 91 year: 2015 end-page: 100 ident: bib0020 article-title: Accelerating haskell on a dataflow architecture: a case study including transactional memory publication-title: CEA – start-page: 141 year: 2013 ident: bib0027 article-title: Fpga code accelerators - the compiler perspective publication-title: DAC – start-page: 137 year: 2014 end-page: 146 ident: bib0024 article-title: Ompss@zynq all-programmable soc ecosystem publication-title: Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays – year: 2002 ident: bib0041 article-title: Experiences using OpenMP based on Compiler Directed Software DSM on a PC Cluster publication-title: Workshop on OpenMP Applications and Tools (WOMPAT’02 – reference: . – year: 2007 ident: bib0031 article-title: HMPP: a hybrid multi-core parallel programming environment publication-title: First Workshop on General Purpose Processing on Graphics Processing Units – start-page: 264 year: 2014 end-page: 269 ident: bib0019 article-title: Simulating a multi-core x86_64 architecture with hardware isa extension supporting a data-flow execution model publication-title: IEEE Proceedings of the AIMS-2014, Madrid, Spain – volume: 45 start-page: 337 year: 2010 end-page: 338 ident: bib0036 article-title: Effective communication and computation overlap with hybrid mpi/smpss publication-title: SIGPLAN Not. – volume: 5568 start-page: 154 year: 2009 end-page: 167 ident: bib0003 article-title: A proposal to extend the openMP tasking model for heterogeneous architectures publication-title: IWOMP – volume: 38 start-page: 976 issue: 8, Part B year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0009 article-title: TERAFLUX: harnessing dataflow in next generation teradevices publication-title: Microprocess. Microsyst. doi: 10.1016/j.micpro.2014.04.001 – volume: 25 start-page: 1489 issue: 6 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0015 article-title: Hybrid dataflow/von-neumann architectures publication-title: IEEE Trans. Parallel Distrib. Syst. doi: 10.1109/TPDS.2013.125 – start-page: 290 year: 2013 ident: 10.1016/j.micpro.2016.07.002_bib0025 article-title: Heterogeneous tasking on smp/fpga socs: The case of ompss and the zynq – volume: 68 start-page: 239 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0048 article-title: A deep analysis on age estimation publication-title: Pattern Recognit. Lett. doi: 10.1016/j.patrec.2015.06.006 – year: 2002 ident: 10.1016/j.micpro.2016.07.002_bib0041 article-title: Experiences using OpenMP based on Compiler Directed Software DSM on a PC Cluster – volume: 45 start-page: 337 issue: 5 year: 2010 ident: 10.1016/j.micpro.2016.07.002_bib0036 article-title: Effective communication and computation overlap with hybrid mpi/smpss publication-title: SIGPLAN Not. doi: 10.1145/1837853.1693502 – ident: 10.1016/j.micpro.2016.07.002_bib0042 – start-page: 127 year: 2010 ident: 10.1016/j.micpro.2016.07.002_bib0026 article-title: Designing modular hardware accelerators in c with roccc 2.0. – start-page: 60 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0010 article-title: An introduction to df-threads and their execution model – start-page: 91 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0020 article-title: Accelerating haskell on a dataflow architecture: a case study including transactional memory – volume: 5568 start-page: 154 year: 2009 ident: 10.1016/j.micpro.2016.07.002_bib0003 article-title: A proposal to extend the openMP tasking model for heterogeneous architectures – year: 2003 ident: 10.1016/j.micpro.2016.07.002_bib0045 article-title: ParADE: an OpenMP Programming Environment for SMP Cluster Systems – ident: 10.1016/j.micpro.2016.07.002_bib0033 doi: 10.2172/862127 – start-page: 3 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0038 article-title: Turning centralized coherence and distributed critical-section execution on their head: A new approach for scalable distributed shared memory – start-page: 1 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0011 article-title: A field experience for a vehicle recognition system using magnetic sensors – start-page: 1 year: 2010 ident: 10.1016/j.micpro.2016.07.002_bib0012 article-title: A multi-pronged approach to benchmark characterization – volume: 21 start-page: 291 issue: 3 year: 2007 ident: 10.1016/j.micpro.2016.07.002_bib0035 article-title: Parallel programmability and the chapel language publication-title: Int. J. High Perform. Comput. Appl. doi: 10.1177/1094342007078442 – ident: 10.1016/j.micpro.2016.07.002_bib0037 – start-page: 62 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0013 article-title: Dynamic power reduction in self-adaptive embedded systems through benchmark analysis – year: 2000 ident: 10.1016/j.micpro.2016.07.002_bib0043 article-title: Jump-dp: A software dsm system with low-latency communication support – ident: 10.1016/j.micpro.2016.07.002_bib0051 – start-page: 303 year: 2012 ident: 10.1016/j.micpro.2016.07.002_bib0007 article-title: iTERAFLUX: exploiting dataflow parallelism in teradevices – start-page: 38 year: 2011 ident: 10.1016/j.micpro.2016.07.002_bib0022 article-title: A fault detection and recovery architecture for a teradevice dataflow system – year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0049 article-title: Real-time pedestrian detection with deep network cascades – ident: 10.1016/j.micpro.2016.07.002_bib0030 – year: 2007 ident: 10.1016/j.micpro.2016.07.002_bib0031 article-title: HMPP: a hybrid multi-core parallel programming environment – start-page: 1 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0023 article-title: Architectural support for fault tolerance in a teradevice dataflow system publication-title: Springer Int’l J. Parallel Program. – start-page: 264 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0019 article-title: Simulating a multi-core x86_64 architecture with hardware isa extension supporting a data-flow execution model – ident: 10.1016/j.micpro.2016.07.002_bib0044 – volume: 6 start-page: 647—658 issue: 5 year: 2006 ident: 10.1016/j.micpro.2016.07.002_bib0046 article-title: Paper running openmp applications efficiently on an everything-shared sdsm publication-title: (JPDC) – ident: 10.1016/j.micpro.2016.07.002_bib0005 – ident: 10.1016/j.micpro.2016.07.002_bib0040 – start-page: 1 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0017 article-title: A matrix multiplier case study for an evaluation of a configurable dataflow-machine – volume: 40 start-page: 519 issue: 10 year: 2005 ident: 10.1016/j.micpro.2016.07.002_bib0034 article-title: X10: an object-oriented approach to non-uniform cluster computing publication-title: SIGPLAN Not. doi: 10.1145/1103845.1094852 – start-page: 1 issue: 0 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0006 article-title: A scalable thread scheduling co-processor based on data-flow principles publication-title: ELSEVIER Future Gener. Comput. Syst. – start-page: 555 year: 2011 ident: 10.1016/j.micpro.2016.07.002_bib0032 article-title: Productive cluster programming with ompss – start-page: 141 year: 2013 ident: 10.1016/j.micpro.2016.07.002_bib0027 article-title: Fpga code accelerators - the compiler perspective – start-page: 272 year: 2013 ident: 10.1016/j.micpro.2016.07.002_bib0018 article-title: The TERAFLUX project: Exploiting the dataflow paradigm in next generation teradevices – start-page: 1 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0008 article-title: Enhancing an x86_64 multi-core architecture with data-flow execution support – ident: 10.1016/j.micpro.2016.07.002_bib0039 – start-page: 675 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0050 article-title: Caffe: convolutional architecture for fast feature embedding – volume: 14 start-page: 794 year: 2015 ident: 10.1016/j.micpro.2016.07.002_bib0021 article-title: Transactional memory on a dataflow architecture for accelerating haskell publication-title: WSEAS Trans. Comput. – start-page: 1701 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0047 article-title: Deepface: Closing the gap to human-level performance in face verification – ident: 10.1016/j.micpro.2016.07.002_bib0029 – year: 2013 ident: 10.1016/j.micpro.2016.07.002_bib0001 – ident: 10.1016/j.micpro.2016.07.002_bib0004 – start-page: 137 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0024 article-title: Ompss@zynq all-programmable soc ecosystem – volume: 23 start-page: 284 issue: 3 year: 2009 ident: 10.1016/j.micpro.2016.07.002_bib0014 article-title: Hierarchical task-based programming with StarSs publication-title: Int. J. High Perform. Comput. Appl. doi: 10.1177/1094342009106195 – start-page: 30 year: 2014 ident: 10.1016/j.micpro.2016.07.002_bib0016 article-title: A clockless computing system based on the static dataflow paradigm – year: 2013 ident: 10.1016/j.micpro.2016.07.002_bib0002 – start-page: 33 year: 2011 ident: 10.1016/j.micpro.2016.07.002_bib0028 article-title: Legup: High-level synthesis for fpga-based processor/accelerator systems |
| SSID | ssj0005062 |
| Score | 2.128221 |
| Snippet | •AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).•The Software Layers developed at the AXIOM project are explained.•OmpSs provides... AXIOM project aims at developing a heterogeneous computing board (SMP-FPGA).The Software Layers developed at the AXIOM project are explained.OmpSs provides an... |
| SourceID | csuc crossref elsevier |
| SourceType | Open Access Repository Enrichment Source Index Database Publisher |
| StartPage | 262 |
| SubjectTerms | Arquitectura de computadors Arquitectures paral·leles Cluster programming Cyber-physical systems Distributed shared memory FPGA Programming Informàtica Microprocessadors Microprocessors Ompss Parallel processing (Electronic computers) Processament en paral·lel (Ordinadors) Smart home Smart video-surveillance Àrees temàtiques de la UPC |
| Title | The AXIOM software layers |
| URI | https://dx.doi.org/10.1016/j.micpro.2016.07.002 https://recercat.cat/handle/2072/272453 |
| Volume | 47 |
| WOSCitedRecordID | wos000390513300003&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVESC databaseName: Elsevier SD Freedom Collection Journals 2021 customDbUrl: eissn: 1872-9436 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0005062 issn: 0141-9331 databaseCode: AIEXJ dateStart: 19950101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Lb9swDBaGdIdd9h6WdRt82GmDBkuWLOsYDB3WAu12yCE3QZblYUXqBnHctfv1JS3ZyRBgL2CHCLESv0iapKmPJCFvhKikr6WiurSCClFbCkZQUgHWyIJ7UKRZaDahzs6KxUJ_idklbd9OQDVNcX2tV_-V1TAHzMbU2b9g93hQmIDvwHQYge0w_jHjZ4vjz6fvWlCx3xHZtbQ3Eeg--KGniMNbhSQBbLeD4fMLnGt3KpgDH3AdvWDLKzjKj4gPWV6Ov85uvnYgIv1ae69Uqy4m6QcEYhv6TJ3Y7mK7eN_5Jqz2WDTJu1EHlsf0uzEUtpcOE6OTDFgd1boPGrVQnGoRqpwMKjcU2Rx0ZlTHwfzy0NVlT7OHIMP5e6AFUAcxeaHqasq3lmzEFyJkjeGFMKwoVmBM54ArqYsJOZgdHy1OtiigtO85O175kF3ZQwD3z_WT9zJxbed2nJgdx2T-kNyPbxTJLEjCI3LHN4_Jg6FbRxKV9xMyBcFIesFIBsFIgmA8JfOPR_MPn2hsjEFdpsWGMi-UqzNWSpU6m-ZW28wrlSrH8lzXmfSae1YpwZWzuayZtmVR1UzC6EGnPyOT5rLxz0lSuQreaMtS1w7cmdLjKrIUJRaxq1TN0inJhvs1LhaNx94lSzOgA89NoJJBKpkU0Qx8Sui41yoUTfnN_98iKQ3YeL92dmOw5vm4gR-eKm644kJmU6IGgpvoJQbvz4Co_PI0L_55z0Nyb_sQvCSTzbrzr8hdd7X51q5fR5m6BcIxh9o |
| linkProvider | Elsevier |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=The+AXIOM+software+layers&rft.jtitle=Microprocessors+and+microsystems&rft.au=%C3%81lvarez%2C+Carlos&rft.au=Ayguad%C3%A9%2C+Eduard&rft.au=Bosch%2C+Jaume&rft.au=Bueno%2C+Javier&rft.date=2016-11-01&rft.pub=Elsevier+B.V&rft.issn=0141-9331&rft.eissn=1872-9436&rft.volume=47&rft.spage=262&rft.epage=277&rft_id=info:doi/10.1016%2Fj.micpro.2016.07.002&rft.externalDocID=S0141933116300850 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0141-9331&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0141-9331&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0141-9331&client=summon |