Hardware Implementation of Polyphase-Decomposition-Based Wavelet Filters for Power System Harmonics Estimation

Computational time and hardware resource are key issues in hardware implementation of any signal-processing algorithm. This paper presents the design and implementation of a polyphase-decomposition-based new architecture of wavelet filter for power system harmonics estimation using discrete wavelet...

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Vydáno v:	IEEE transactions on instrumentation and measurement Ročník 65; číslo 7; s. 1585 - 1595
Hlavní autoři:	Tiwari, Vinay K., Jain, Sachin K.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	New York IEEE 01.07.2016 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Architecture Architecture (computers) Boards Computation Discrete wavelet packet transform (DWPT) Discrete wavelet transforms Estimation field-programming gate array (FPGA) finite impulse response (FIR) filter Finite impulse response filters Hardware Harmonic analysis Harmonics Instrumentation Power harmonic filters power quality (PQ) root mean square (rms) Wavelet Xilinx system generator (XSG) root mean square (rms) finite impulse response (FIR) filter Xilinx system generator (XSG) power quality (PQ) Discrete wavelet packet transform (DWPT) field-programming gate array (FPGA)
ISSN:	0018-9456, 1557-9662
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Popis
Shrnutí:	Computational time and hardware resource are key issues in hardware implementation of any signal-processing algorithm. This paper presents the design and implementation of a polyphase-decomposition-based new architecture of wavelet filter for power system harmonics estimation using discrete wavelet packet transform (DWPT). Usually, DWPT provides coefficients as the output; however, the proposed architecture also includes provision for providing root mean square values directly. The proposed method reduces computational requirements and save memory resources. Xilinx system generator, a higher abstraction level tool, has been used to simulate and implement the proposed scheme on the Xilinx Artix-7 field-programming gate array AC701 board. Performance of the proposed architecture has been validated and compared through hardware cosimulation with variety of synthetic and experimental signals.
Bibliografie:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 content type line 23
ISSN:	0018-9456 1557-9662
DOI:	10.1109/TIM.2016.2540861