Decimator systolic arrays design space exploration for multirate signal processing applications

This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained...

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Vydané v:	IET circuits, devices & systems Ročník 13; číslo 8; s. 1232 - 1240
Hlavní autori:	Shoukry, Mohammed, Gebali, Fayez, Agathoklis, Panajotis
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	Stevenage The Institution of Engineering and Technology 01.11.2019 John Wiley & Sons, Inc
Predmet:	Algorithms antialiasing antialiasing FIR filter Commutators decimation factor decimator implementation decimator systolic arrays design space exploration dependence graph Design downsampler downsampling fastest design Field programmable gate arrays field-programmable gate array implementations filtering theory FIR filter coefficients FIR filters Fourier transforms Gate arrays known decimator designs multirate signal processing applications polyphase antialiasing filter polyphase design Power projection operations Research Article Scheduling Signal processing Space exploration systematic methodology systolic array design options systolic array structure Systolic arrays downsampler polyphase design systolic array structure field programmable gate arrays signal processing filtering theory decimator systolic arrays design space exploration decimator implementation systolic arrays systolic array design options multirate signal processing applications field-programmable gate array implementations projection operations antialiasing FIR filters systematic methodology dependence graph downsampling FIR filter coefficients fastest design decimation factor polyphase antialiasing filter known decimator designs antialiasing FIR filter
ISSN:	1751-858X, 1751-8598, 1751-8598
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Popis
Shrnutí:	This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Field-programmable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.
Bibliografia:	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ISSN:	1751-858X 1751-8598 1751-8598
DOI:	10.1049/iet-cds.2019.0077