Chen, X., Kang, J., Lin, S., & Akella, V. (2011). Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. IEEE transactions on circuits and systems. I, Regular papers, 58(1), 98-111. https://doi.org/10.1109/TCSI.2010.2055250
Citace podle Chicago (17th ed.)Chen, Xiaoheng, Jingyu Kang, Shu Lin, a Venkatesh Akella. "Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders." IEEE Transactions on Circuits and Systems. I, Regular Papers 58, no. 1 (2011): 98-111. https://doi.org/10.1109/TCSI.2010.2055250.
Citace podle MLA (9th ed.)Chen, Xiaoheng, et al. "Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders." IEEE Transactions on Circuits and Systems. I, Regular Papers, vol. 58, no. 1, 2011, pp. 98-111, https://doi.org/10.1109/TCSI.2010.2055250.