Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled...

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Bibliographic Details
Published in:International journal of parallel programming Vol. 45; no. 3; pp. 530 - 550
Main Authors: Garcia, Victor, Rico, Alejandro, Villavieja, Carlos, Carpenter, Paul, Navarro, Nacho, Ramirez, Alex
Format: Journal Article Publication
Language:English
Published: New York Springer US 01.06.2017
Springer Nature B.V
Subjects:
Analysis
Arquitectura de computadors
Benchmarks
Cache
Cache memories
Cache memory
Central processing units
Computer programming
Computer programs
Computer Science
CPUs
Dynamical systems
Engine blocks
Engines
Gestió de memòria (Informàtica)
Hardware
Informàtica
Memòria cau
Prefetch
Processor Architectures
Schedules
Software
Software Engineering/Programming and Operating Systems
Stall
Studies
Task based programming models
Theory of Computation
Àrees temàtiques de la UPC
Prefetch
Cache memories
Task based programming models
ISSN:0885-7458, 1573-7640
Online Access:Get full text
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Summary:Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.
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ISSN:0885-7458
1573-7640
DOI:10.1007/s10766-016-0431-8