Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled...

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Vydáno v:	International journal of parallel programming Ročník 45; číslo 3; s. 530 - 550
Hlavní autoři:	Garcia, Victor, Rico, Alejandro, Villavieja, Carlos, Carpenter, Paul, Navarro, Nacho, Ramirez, Alex
Médium:	Journal Article Publikace
Jazyk:	angličtina
Vydáno:	New York Springer US 01.06.2017 Springer Nature B.V
Témata:	Analysis Arquitectura de computadors Benchmarks Cache Cache memories Cache memory Central processing units Computer programming Computer programs Computer Science CPUs Dynamical systems Engine blocks Engines Gestió de memòria (Informàtica) Hardware Informàtica Memòria cau Prefetch Processor Architectures Schedules Software Software Engineering/Programming and Operating Systems Stall Studies Task based programming models Theory of Computation Àrees temàtiques de la UPC Prefetch Cache memories Task based programming models
ISSN:	0885-7458, 1573-7640
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Abstract	Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.
AbstractList	Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution. Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution. Peer Reviewed Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtime-directed prefetching and more specifically runtime-directed block prefetching. This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to. Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32 and 10 % on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18 and 3 % on average in energy-to-solution.
Author	Ramirez, Alex Rico, Alejandro Garcia, Victor Villavieja, Carlos Navarro, Nacho Carpenter, Paul
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SubjectTerms	Analysis Arquitectura de computadors Benchmarks Cache Cache memories Cache memory Central processing units Computer programming Computer programs Computer Science CPUs Dynamical systems Engine blocks Engines Gestió de memòria (Informàtica) Hardware Informàtica Memòria cau Prefetch Processor Architectures Schedules Software Software Engineering/Programming and Operating Systems Stall Studies Task based programming models Theory of Computation Àrees temàtiques de la UPC
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Title	Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors
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