A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control
This paper presents a hardware architecture for embedded real-time model predictive control (MPC). The computational cost of an MPC problem, which relies on the solution of an optimization problem at every time step, is dominated by operations on real matrices. In order to design an efficient and lo...
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| Published in: | IEEE transactions on control systems technology Vol. 17; no. 5; pp. 1006 - 1017 |
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| Main Authors: | , , , |
| Format: | Journal Article |
| Language: | English |
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New York, NY
IEEE
01.09.2009
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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| ISSN: | 1063-6536, 1558-0865 |
| Online Access: | Get full text |
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| Abstract | This paper presents a hardware architecture for embedded real-time model predictive control (MPC). The computational cost of an MPC problem, which relies on the solution of an optimization problem at every time step, is dominated by operations on real matrices. In order to design an efficient and low-cost application-specific processor, we analyze the computational cost of MPC, and we propose a limited-resource host processor to be connected with an application-specific matrix coprocessor. The coprocessor uses a 16-b logarithmic number system arithmetic unit, which is designed using cotransformation, to carry out the required arithmetic operations. The proposed architecture is implemented by means of a hardware description language and then prototyped and emulated on a field-programmable gate array. Results on computation time and architecture area are presented and analyzed, and the functionality of the proposed architecture is verified using two case studies: a linear problem of a rotating antenna and a nonlinear glucose-regulation problem. The proposed MPC architecture yields a small-in-size and energy-efficient implementation that is capable of solving the aforementioned problems on the order of milliseconds, and we compare its performance and area requirements with other MPC designs that have appeared in the literature. |
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| AbstractList | This paper presents a hardware architecture for embedded real-time model predictive control (MPC). The computational cost of an MPC problem, which relies on the solution of an optimization problem at every time step, is dominated by operations on real matrices. In order to design an efficient and low-cost application-specific processor, we analyze the computational cost of MPC, and we propose a limited-resource host processor to be connected with an application-specific matrix coprocessor. The coprocessor uses a 16-b logarithmic number system arithmetic unit, which is designed using cotransformation, to carry out the required arithmetic operations. The proposed architecture is implemented by means of a hardware description language and then prototyped and emulated on a field-programmable gate array. Results on computation time and architecture area are presented and analyzed, and the functionality of the proposed architecture is verified using two case studies: a linear problem of a rotating antenna and a nonlinear glucose-regulation problem. The proposed MPC architecture yields a small-in-size and energy-efficient implementation that is capable of solving the aforementioned problems on the order of milliseconds, and we compare its performance and area requirements with other MPC designs that have appeared in the literature. The computational cost of an MPC problem, which relies on the solution of an optimization problem at every time step, is dominated by operations on real matrices. |
| Author | Bleris, L.G. Arnold, M.G. Kothare, M.V. Vouzis, P.D. |
| Author_xml | – sequence: 1 givenname: P.D. surname: Vouzis fullname: Vouzis, P.D. organization: Comput. Archit. & Arithmetic Res. Lab., Lehigh Univ., Bethlehem, PA, USA – sequence: 2 givenname: M.V. surname: Kothare fullname: Kothare, M.V. – sequence: 3 givenname: L.G. surname: Bleris fullname: Bleris, L.G. – sequence: 4 givenname: M.G. surname: Arnold fullname: Arnold, M.G. |
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| Keywords | Description language Processor Arithmetics Logarithmic function Non linear control Field programmable gate array Real time Optimization model predictive control (MPC) Circuit architecture Boarded computer Model predictive control Embedded systems Coprocessor Performance requirement Optimal control logarithmic number system (LNS) Arithmetic operation Custom circuit system-on-chip Microdevice Antenna Real matrix |
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| SubjectTerms | Algorithms Application specific processors Applied sciences Architecture Arithmetic Computational efficiency Computer architecture Computer science; control theory; systems Control theory. Systems Coprocessors Design Design engineering Embedded systems Exact sciences and technology Hardware logarithmic number system (LNS) Mathematical models Microdevice Microprocessors model predictive control (MPC) Optimal control Predictive control Predictive models Real time Real time systems Studies System-on-a-chip system-on-chip |
| Title | A System-on-a-Chip Implementation for Embedded Real-Time Model Predictive Control |
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