Evolutionary multi-level acyclic graph partitioning

Directed graphs are widely used to model data flow and execution dependencies in streaming applications. This enables the utilization of graph partitioning algorithms for the problem of parallelizing execution on multiprocessor architectures under hardware resource constraints. However due to progra...

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Vydané v:Journal of heuristics Ročník 26; číslo 5; s. 771 - 799
Hlavní autori: Moreira, Orlando, Popp, Merten, Schulz, Christian
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York Springer US 01.10.2020
Springer Nature B.V
Predmet:
Artificial Intelligence
Calculus of Variations and Optimal Control; Optimization
Compilers
Constraints
Embedded systems
Evolutionary algorithms
Genetic algorithms
Graph theory
Graphs
Hardware
Heuristic
Management Science
Mathematics
Mathematics and Statistics
Multiprocessing
Operations Research
Operations Research/Decision Theory
Parallel processing
Partitioning
Reduction
Graph partitioning
Computer vision
Embedded systems
Evolutionary algorithm
Imaging
ISSN:1381-1231, 1572-9397
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Shrnutí:Directed graphs are widely used to model data flow and execution dependencies in streaming applications. This enables the utilization of graph partitioning algorithms for the problem of parallelizing execution on multiprocessor architectures under hardware resource constraints. However due to program memory restrictions in embedded multiprocessor systems, applications need to be divided into parts without cyclic dependencies. We found that this can be done by a subsequent second graph partitioning step with an additional acyclicity constraint. We have four main contributions. First, we show that this more constrained version of the graph partitioning problem is NP-complete and present linear time heuristics. We then integrate them into an existing multi-level graph partitioning framework to better handle large graphs. This achieves a 9% reduction of the edge cut compared to the previous single-level algorithm. Based on this, we engineer an evolutionary algorithm to further reduce the cut, achieving a 30% reduction on average compared to the state of the art. Finally, we integrate the partitioning heuristics into a graph compiler for an embedded multiprocessor architecture and show that this can reduce the amount of communication for a real-world imaging application and thereby accelerate it by an average of 11%. It is shown that the compiler can emit optimized code for vastly different hardware platforms using the heuristics. In addition, we demonstrate how a custom fitness function for the evolutionary algorithm can be used to optimize other objectives like load balancing if the communication volume is not predominantly important on a given hardware platform.
Bibliografia:ObjectType-Article-1
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ISSN:1381-1231
1572-9397
DOI:10.1007/s10732-020-09448-8