Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures

The introduction of General-Purpose computation on GPUs (GPGPUs) has changed the landscape for the future of parallel computing. At the core of this phenomenon are massively multithreaded, data-parallel architectures possessing impressive acceleration ratings, offering low-cost supercomputing togeth...

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Bibliographic Details
Published in:	IEEE transactions on parallel and distributed systems Vol. 22; no. 1; pp. 105 - 118
Main Authors:	Byunghyun Jang, Schaa, Dana, Mistry, Perhaad, Kaeli, David
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.01.2011 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Acceleration Architecture Benchmarking Computation Computer architecture Concurrent computing data parallelism data-parallel architectures Delay General-purpose computation on GPUs (GPGPUs) GPU computing Graphics processing unit Kernel Kernels Logic design memory access pattern memory coalescing memory optimization memory selection Microprocessors Parallel architectures Parallel processing Performance enhancement Transformations vectorization
ISSN:	1045-9219, 1558-2183
Online Access:	Get full text
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