High-throughput LDPC decoders
A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding al...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems Jg. 11; H. 6; S. 976 - 996 |
|---|---|
| Hauptverfasser: | , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
Piscataway, NJ
IEEE
01.12.2003
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 1063-8210, 1557-9999 |
| Online-Zugang: | Volltext |
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| Abstract | A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length. |
|---|---|
| AbstractList | [...] the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The architecture benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, decoding algorithm, and decoder architecture. First, the interconnect complexity problem of current decoder implementations is mitigated by designing architecture-aware LDPC codes having embedded structural regularity features that result in a regular and scalable message-transport network with reduced control overhead. Second, the memory overhead problem in current day decoders is reduced by more than 75% by employing a new turbo decoding algorithm for LDPC codes that removes the multiple checkto-bit message update bottleneck of the current algorithm. A new merged-schedule merge-passing algorithm is also proposed that reduces the memory overhead of the current algorithm for low to moderate-throughput decoders. Moreover, a parallel soft-input-soft-output (SISO) message update mechanism is proposed that implements the recursions of the Balh-Cocke-Jelinek-Raviv (BCJR) algorithm in terms of simple "max-quartet" operations that do not require lookup-tables and incur negligible loss in performance compared to the ideal case. Finally, an efficient programmable architecture coupled with a scalable and dynamic transport network for storing and routing messages is proposed, and a full-decoder architecture is presented. Simulations demonstrate that the proposed architecture attains a throughput of 1.92 Gb/s for a frame length of 2304 bits, and achieves savings of 89.13% and 69.83% in power consumption and silicon area over state-of-the-art, with a reduction of 60.5% in interconnect length. |
| Author | Shanbhag, N.R. Mansour, M.M. |
| Author_xml | – sequence: 1 givenname: M.M. surname: Mansour fullname: Mansour, M.M. organization: Univ. of Illinois, Urbana, IL, USA – sequence: 2 givenname: N.R. surname: Shanbhag fullname: Shanbhag, N.R. |
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| Keywords | Performance evaluation Input output State of the art Updating Implementation Optimization Coding soft-input soft-output (SISO) decoder Ramanujan graphs VLSI decoder architectures Message transmission VLSI circuit turbo decoding algorithm System design Decoding circuit Turbo code Algorithm Index Terms-Low-density parity-check (LDPC) codes Look up table Circuit architecture Boarded computer Power consumption Interconnection Integrated circuit Parity check |
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| SubjectTerms | Algorithm design and analysis Algorithms Applied sciences Architecture Codes Decoders Decoding Design optimization Design. Technologies. Operation analysis. Testing Electronics Energy consumption Exact sciences and technology Integrated circuits Low density parity check codes Memory architecture Messages Networks Parity check codes Performance loss Reduction Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Throughput Very large scale integration |
| Title | High-throughput LDPC decoders |
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