Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant t...

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Vydáno v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 11; číslo 6; s. 1120 - 1135
Hlavní autoři:	Adya, S.N., Markov, I.L.
Médium:	Journal Article
Jazyk:	angličtina
Vydáno:	Piscataway, NJ IEEE 01.12.2003 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:	Application specific integrated circuits Applied sciences Computation Computational modeling Context modeling Design automation Design engineering Design. Technologies. Operation analysis. Testing Electronics Empirical analysis Exact sciences and technology Floorplans Integrated circuits Mathematical analysis Nonhomogeneous media Operations research Pins Representations Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shape Simulated annealing Studies Very large scale integration physical design VLSI circuit Circuit design hierachical design Index Terms-Floorplanning VLSI CAD System on a chip Aspect ratio Algorithm Implementation Optimization Computation time Integrated circuit layout Linear combination Integrated circuit Simulated annealing Objective function Miniaturization placement Custom circuit Computer aided design
ISSN:	1063-8210, 1557-9999
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