Fixed-outline floorplanning: enabling hierarchical design
Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant t...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems Jg. 11; H. 6; S. 1120 - 1135 |
|---|---|
| Hauptverfasser: | , |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
Piscataway, NJ
IEEE
01.12.2003
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 1063-8210, 1557-9999 |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Abstract | Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm. |
|---|---|
| AbstractList | Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. |
| Author | Adya, S.N. Markov, I.L. |
| Author_xml | – sequence: 1 givenname: S.N. surname: Adya fullname: Adya, S.N. organization: Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA – sequence: 2 givenname: I.L. surname: Markov fullname: Markov, I.L. organization: Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA |
| BackLink | http://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=15397623$$DView record in Pascal Francis |
| BookMark | eNp9kUtrGzEUhUVJIM7jB4RuTKHpalxJV49RdyXUScCQRdJshUa-YytMJFcaQ_PvK9cBQxbRRkJ859x7OKfkKKaIhFwyOmOMmu-PT4uHuxmnFGYt01KoT2TCpNSNqeeovqmCpuWMnpDTUp4pZUIYOiFmHv7isknbcQgRp_2QUt4MLsYQVz-mGF1X_1fTdcDssl8H74bpEktYxXNy3Luh4MXbfUZ-z389Xt82i_ubu-ufi8ZDC2OjQEBngHeOdhoQlgyMZhIl522nqIBWdBI6zp32ne6XqDyvkObeGy16DWfk2953k9OfLZbRvoTicahLYtoWa6g2QrfSVPLqQ5K3wJTSO8sv78DntM2xprCGM6GBclahr2-QKzV1n130odhNDi8uv1omaw7FoXJsz_mcSsnYHxBqd93Y_93YXTd2303V6HcaH0Y3hhTH7MLwofLzXhkQ8TCJSylaBf8AqdicRA |
| CODEN | IEVSE9 |
| CitedBy_id | crossref_primary_10_1109_TVLSI_2016_2562361 crossref_primary_10_1155_2011_530851 crossref_primary_10_1109_TCAD_2010_2041850 crossref_primary_10_1109_TCAD_2009_2015738 crossref_primary_10_1002_cta_1939 crossref_primary_10_1016_j_ejor_2012_08_006 crossref_primary_10_1109_TVLSI_2010_2050012 crossref_primary_10_1109_TCAD_2009_2013273 crossref_primary_10_1109_TCAD_2009_2017079 crossref_primary_10_1109_TCAD_2010_2061610 crossref_primary_10_1007_s00004_024_00802_y crossref_primary_10_4316_AECE_2013_01002 crossref_primary_10_1049_iet_cds_2009_0049 crossref_primary_10_1109_TCAD_2005_855981 crossref_primary_10_1007_s12652_017_0661_7 crossref_primary_10_1016_j_vlsi_2022_04_001 crossref_primary_10_1109_TCAD_2011_2149870 crossref_primary_10_1002_cta_829 crossref_primary_10_1016_j_asoc_2013_02_011 crossref_primary_10_3233_JIFS_152551 crossref_primary_10_1109_ACCESS_2019_2942839 crossref_primary_10_1109_TCAD_2022_3213609 crossref_primary_10_4218_etrij_14_0113_1233 crossref_primary_10_1007_s11227_011_0599_z crossref_primary_10_1016_j_vlsi_2024_102293 crossref_primary_10_1002_cta_3672 crossref_primary_10_1007_s10878_008_9148_y crossref_primary_10_1109_TVLSI_2008_2011205 crossref_primary_10_1109_TCAD_2005_859519 crossref_primary_10_1109_TVLSI_2008_2009304 crossref_primary_10_1016_j_sysarc_2018_07_002 crossref_primary_10_3390_electronics13091696 crossref_primary_10_1109_TCAD_2008_917968 crossref_primary_10_1109_TCAD_2010_2072730 crossref_primary_10_1145_2535575 crossref_primary_10_1109_TVLSI_2006_871763 crossref_primary_10_1587_transfun_E95_A_1529 crossref_primary_10_1016_j_mcm_2009_08_026 crossref_primary_10_1142_S021812662550286X crossref_primary_10_1007_s10878_015_9973_8 crossref_primary_10_1016_j_cor_2021_105225 crossref_primary_10_1002_cta_2178 crossref_primary_10_1016_j_asoc_2015_10_045 crossref_primary_10_1109_TCAD_2011_2179041 crossref_primary_10_1049_iet_cdt_2013_0118 crossref_primary_10_1016_j_engappai_2006_10_006 crossref_primary_10_3390_electronics7110325 crossref_primary_10_1109_TCAD_2023_3346284 crossref_primary_10_1109_TC_2010_211 crossref_primary_10_1016_j_entcs_2008_02_003 crossref_primary_10_1016_j_vlsi_2008_08_001 crossref_primary_10_1109_TVLSI_2009_2024118 crossref_primary_10_1016_j_vlsi_2010_04_001 crossref_primary_10_1145_3676845 crossref_primary_10_1007_s11227_022_04444_0 crossref_primary_10_1007_s11767_008_0025_8 crossref_primary_10_1109_TCAD_2018_2864291 crossref_primary_10_1007_s10589_011_9442_y crossref_primary_10_1109_TCAD_2013_2244642 crossref_primary_10_1016_j_mejo_2012_03_005 crossref_primary_10_1145_1391962_1391975 crossref_primary_10_1109_TCAD_2005_855969 crossref_primary_10_1049_iet_cds_2013_0003 crossref_primary_10_1109_TCAD_2007_907065 crossref_primary_10_1049_iet_cds_2011_0350 crossref_primary_10_1007_s00034_019_01054_9 crossref_primary_10_1631_FITEE_1500386 crossref_primary_10_1109_TCAD_2005_862748 crossref_primary_10_1145_1497561_1497563 crossref_primary_10_1109_TCAD_2006_882590 crossref_primary_10_1109_TMSCS_2016_2637345 crossref_primary_10_1109_TETC_2017_2703784 crossref_primary_10_1109_TVLSI_2011_2104983 crossref_primary_10_1145_2187671_2187675 crossref_primary_10_1145_2567940 crossref_primary_10_1016_j_mejo_2014_01_006 crossref_primary_10_1109_TCAD_2012_2228267 crossref_primary_10_1016_j_vlsi_2015_07_017 crossref_primary_10_1049_iet_cdt_20070012 crossref_primary_10_1016_j_vlsi_2007_12_002 crossref_primary_10_1109_TCAD_2012_2228304 crossref_primary_10_1145_1857927_1857934 crossref_primary_10_1145_1862648_1862654 crossref_primary_10_1109_TVLSI_2008_2001734 crossref_primary_10_1109_ACCESS_2019_2956595 crossref_primary_10_1109_TCAD_2007_891368 crossref_primary_10_1109_TVLSI_2008_2011240 crossref_primary_10_1016_j_compeleceng_2024_109784 crossref_primary_10_1016_j_cor_2017_03_011 crossref_primary_10_1016_j_engappai_2012_04_007 crossref_primary_10_1016_j_vlsi_2016_11_006 crossref_primary_10_1016_j_micpro_2011_05_002 crossref_primary_10_1145_1044111_1044116 crossref_primary_10_1109_TCAD_2011_2106851 crossref_primary_10_1109_TCAD_2008_925792 crossref_primary_10_1016_j_vlsi_2012_02_006 crossref_primary_10_1587_transele_E96_C_501 crossref_primary_10_1016_j_suscom_2012_01_004 crossref_primary_10_1109_TCAD_2006_870076 crossref_primary_10_1007_s00034_015_0020_x crossref_primary_10_1016_j_mejo_2022_105536 crossref_primary_10_1155_2011_483681 crossref_primary_10_1080_03052150801901475 crossref_primary_10_1109_TCAD_2014_2351571 crossref_primary_10_1002_cpe_2957 crossref_primary_10_1049_iet_cds_2020_0128 crossref_primary_10_1016_j_vlsi_2017_06_013 crossref_primary_10_1016_j_mejo_2010_08_022 crossref_primary_10_1016_j_vlsi_2008_09_003 crossref_primary_10_1109_TCAD_2008_2009167 crossref_primary_10_1109_TCAD_2007_907271 crossref_primary_10_1109_ACCESS_2020_2980135 crossref_primary_10_1109_TVLSI_2019_2905626 crossref_primary_10_1109_TCAD_2011_2114531 crossref_primary_10_1007_s10479_008_0460_9 crossref_primary_10_1049_iet_cdt_2008_0095 crossref_primary_10_1109_TCAD_2005_860957 crossref_primary_10_1007_s11390_010_9319_z crossref_primary_10_1145_1412587_1412591 crossref_primary_10_1145_1970353_1970356 crossref_primary_10_1145_1278349_1278350 crossref_primary_10_1145_1562514_1562519 crossref_primary_10_1145_2457443_2457448 crossref_primary_10_1109_TCAD_2006_888284 crossref_primary_10_1145_3149817 crossref_primary_10_1109_MDT_2008_138 crossref_primary_10_1109_TCAD_2024_3408106 crossref_primary_10_1109_TCAD_2008_925775 crossref_primary_10_1016_j_sysarc_2013_09_001 |
| Cites_doi | 10.1145/504914.504922 10.1145/274535.274560 10.1109/81.536741 10.1109/ICCAD.1999.810675 10.1109/ICCD.2001.955047 10.1109/43.552084 10.1145/332357.332401 10.1109/ASPDAC.2003.1195102 10.1145/332357.332395 10.1145/640000.640030 10.1145/337292.337547 10.1145/1119772.1119916 10.1145/332357.332396 10.1145/378239.379062 10.1109/DATE.1999.761186 10.1145/337292.337541 10.1145/370155.370523 10.1145/343647.343713 10.1145/337292.337549 10.1109/ASPDAC.2003.1195100 10.1145/309847.309955 10.1145/505388.505392 |
| ContentType | Journal Article |
| Copyright | 2004 INIST-CNRS Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2003 |
| Copyright_xml | – notice: 2004 INIST-CNRS – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2003 |
| DBID | RIA RIE AAYXX CITATION IQODW 7SP 8FD L7M F28 FR3 |
| DOI | 10.1109/TVLSI.2003.817546 |
| DatabaseName | IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE/IET Electronic Library CrossRef Pascal-Francis Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace ANTE: Abstracts in New Technology & Engineering Engineering Research Database |
| DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts Engineering Research Database ANTE: Abstracts in New Technology & Engineering |
| DatabaseTitleList | Engineering Research Database Technology Research Database Technology Research Database |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Applied Sciences |
| EISSN | 1557-9999 |
| EndPage | 1135 |
| ExternalDocumentID | 2586703611 15397623 10_1109_TVLSI_2003_817546 1255486 |
| GroupedDBID | -~X .DC 0R~ 29I 3EH 4.4 5GY 5VS 6IK 97E AAJGR AARMG AASAJ AAWTH ABAZT ABFSI ABQJQ ABVLG ACGFS ACIWK AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 E.L EBS EJD HZ~ H~9 ICLAB IEDLZ IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P RIA RIE RNS TN5 VH1 AAYXX CITATION IQODW RIG 7SP 8FD L7M F28 FR3 |
| ID | FETCH-LOGICAL-c383t-6343b932ba0b73e3d139715e5228b604384b53b22a7cb7fde6c23d172cc974f73 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 243 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000188222700014&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1063-8210 |
| IngestDate | Sun Sep 28 12:05:35 EDT 2025 Mon Sep 29 05:00:41 EDT 2025 Fri Jul 25 06:06:26 EDT 2025 Mon Jul 21 09:16:22 EDT 2025 Sat Nov 29 08:02:02 EST 2025 Tue Nov 18 22:08:49 EST 2025 Tue Aug 26 16:38:26 EDT 2025 |
| IsDoiOpenAccess | false |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 6 |
| Keywords | physical design VLSI circuit Circuit design hierachical design Index Terms-Floorplanning VLSI CAD System on a chip Aspect ratio Algorithm Implementation Optimization Computation time Integrated circuit layout Linear combination Integrated circuit Simulated annealing Objective function Miniaturization placement Custom circuit Computer aided design |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html CC BY 4.0 |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c383t-6343b932ba0b73e3d139715e5228b604384b53b22a7cb7fde6c23d172cc974f73 |
| Notes | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14 ObjectType-Article-2 ObjectType-Feature-1 content type line 23 |
| PQID | 921473021 |
| PQPubID | 23500 |
| PageCount | 16 |
| ParticipantIDs | proquest_miscellaneous_907947859 proquest_miscellaneous_28316677 crossref_primary_10_1109_TVLSI_2003_817546 proquest_journals_921473021 crossref_citationtrail_10_1109_TVLSI_2003_817546 ieee_primary_1255486 pascalfrancis_primary_15397623 |
| PublicationCentury | 2000 |
| PublicationDate | 2003-12-01 |
| PublicationDateYYYYMMDD | 2003-12-01 |
| PublicationDate_xml | – month: 12 year: 2003 text: 2003-12-01 day: 01 |
| PublicationDecade | 2000 |
| PublicationPlace | Piscataway, NJ |
| PublicationPlace_xml | – name: Piscataway, NJ – name: New York |
| PublicationTitle | IEEE transactions on very large scale integration (VLSI) systems |
| PublicationTitleAbbrev | TVLSI |
| PublicationYear | 2003 |
| Publisher | IEEE Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: Institute of Electrical and Electronics Engineers – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref13 ref12 ref14 ref2 ref1 ref17 ref16 ref19 Scheffer (ref18) ref23 Hong (ref11) ref20 ref22 ref21 ref28 ref27 Pang (ref24) ref29 ref8 ref7 Fujuyoshi (ref10) ref9 Sherwani (ref26) 1999 ref4 ref3 Lackey (ref15) ref6 ref5 Remond (ref25) |
| References_xml | – start-page: 103 volume-title: Proc. ISPD 1999 ident: ref10 article-title: Arbitrary convex and concave rectilinear block packing using sequence pair – volume-title: Algorithms For VLSI Design Automation year: 1999 ident: ref26 – ident: ref12 doi: 10.1145/504914.504922 – ident: ref21 doi: 10.1145/274535.274560 – ident: ref19 doi: 10.1109/81.536741 – ident: ref7 doi: 10.1109/ICCAD.1999.810675 – ident: ref2 doi: 10.1109/ICCD.2001.955047 – ident: ref20 doi: 10.1109/43.552084 – ident: ref13 doi: 10.1145/332357.332401 – ident: ref16 doi: 10.1109/ASPDAC.2003.1195102 – ident: ref23 doi: 10.1145/332357.332395 – volume-title: DAC 02 ident: ref25 article-title: Monterey usage at STMicroelectronics – ident: ref9 doi: 10.1145/640000.640030 – ident: ref6 doi: 10.1145/337292.337547 – ident: ref8 doi: 10.1145/1119772.1119916 – start-page: 464 volume-title: Proc. DAC 2000 ident: ref24 article-title: Block placement with symmetry constraint based on the O-tree nonslicing representation – ident: ref29 doi: 10.1145/332357.332396 – ident: ref17 doi: 10.1145/378239.379062 – volume-title: Proc. IEEE/DATC Electronic Design Process Workshop ident: ref15 article-title: Design planning methodology for rapid chip deployment – ident: ref22 doi: 10.1109/DATE.1999.761186 – ident: ref5 doi: 10.1145/337292.337541 – volume-title: Proc. IEEE/DATC Electronic Design Process Workshop ident: ref18 article-title: Data modeling and convergence methodology in integration ensemble – ident: ref28 doi: 10.1145/370155.370523 – ident: ref27 doi: 10.1145/343647.343713 – ident: ref4 doi: 10.1145/337292.337549 – ident: ref14 doi: 10.1109/ASPDAC.2003.1195100 – ident: ref3 doi: 10.1145/309847.309955 – ident: ref1 doi: 10.1145/505388.505392 – start-page: 8 volume-title: Proc. ICCAD 2000 ident: ref11 article-title: Corner block list: An effective and efficient topological representation of nonslicing floorplan |
| SSID | ssj0014490 |
| Score | 2.249829 |
| Snippet | Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation,... When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. |
| SourceID | proquest pascalfrancis crossref ieee |
| SourceType | Aggregation Database Index Database Enrichment Source Publisher |
| StartPage | 1120 |
| SubjectTerms | Application specific integrated circuits Applied sciences Computation Computational modeling Context modeling Design automation Design engineering Design. Technologies. Operation analysis. Testing Electronics Empirical analysis Exact sciences and technology Floorplans Integrated circuits Mathematical analysis Nonhomogeneous media Operations research Pins Representations Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shape Simulated annealing Studies Very large scale integration |
| Title | Fixed-outline floorplanning: enabling hierarchical design |
| URI | https://ieeexplore.ieee.org/document/1255486 https://www.proquest.com/docview/921473021 https://www.proquest.com/docview/28316677 https://www.proquest.com/docview/907947859 |
| Volume | 11 |
| WOSCitedRecordID | wos000188222700014&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1557-9999 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0014490 issn: 1063-8210 databaseCode: RIE dateStart: 19930101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3dSxwxEB_06IM-qO1VXL-6Dz6VRveS3Xz4JtKjhSIFr-LbkmSzIBy3x32If74z2fW0WAu-hc0EwuRjfrMzmR_AiUUjwL3RrOYuZ3nhBbPW1syZQvNQVwNf60g2oa6u9O2t-b0G31ZvYUIIMfksnFIzxvKrxi_pV9kZGmME2HId1pWS7VutVcQgz01beUAKptGP6SKYg8ycjW5-Xf-MpT9PNVpLwrovbFAkVaGUSDtHrdQtncWrmzmam-H2-ya6A1sdrEwv2n3wEdbC5BNsvig22AczvHsIFaMMIPyY1uOmmU07yqLzNNAbKmylxI0dows4zbSK-R2f4c_w--jyB-uIE5hHh3PBpMiFQ2DmbOaUCKIimDcoAmIt7STF_nJXCMe5Vd6pugrScxRS3Ht0L2oldqE3aSZhjzKfqsw5Xnkvea6tsHhoUUL6zIaglE4ge1Jl6buq4kRuMS6jd5GZMmqf2C5F2Wo_ga-rIdO2pMb_hPuk3mfBVrMJHP-1Xs_9BQEsLhI4eFrAsjuV89IQKZNAVJPAl1UvHieKkdhJaJbzEtHWQEqlEkjfkDAZXmFKF2b_31M7gI024Y9SXg6ht5gtwxF88PeLu_nsOG7aR3mV6dk |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3dSxwxEB_0Ktg-tPWjuLXVfeiTNLqX7Oajb6X0UHoeQs_i25JksyDIrdyH9M_vTHbvVGyFvoXNBMLkY36zM5kfwCeLRoB7o1nNXc7ywgtmra2ZM4Xmoa76vtaRbEKNRvrqylyswefVW5gQQkw-C8fUjLH8qvEL-lV2gsYYAbZchxfEnNW91lrFDPLctLUHpGAaPZkuhtnPzMn41_DnWSz-eazRXhLafWCFIq0KJUXaGeqlbgktntzN0eAM3vzfVN_C6w5Ypl_bnbAFa2GyDa8elBvcATO4_h0qRjlA-DGtb5pmetuRFn1JA72iwlZK7NgxvoDTTKuY4bELl4Pv42-nrKNOYB5dzjmTIhcOoZmzmVMiiIqAXr8IiLa0kxT9y10hHOdWeafqKkjPUUhx79HBqJV4B71JMwl7lPtUZc7xynvJc22FxWOLEtJnNgSldALZUpWl7-qKE73FTRn9i8yUUfvEdynKVvsJHK2G3LZFNZ4T3iH13gu2mk3g4NF63fcXBLG4SGB_uYBldy5npSFaJoG4JoHDVS8eKIqS2EloFrMS8VZfSqUSSP8hYTK8xJQuzPu_T-0QNk_H58NyeDb6sQ8v2_Q_SoD5AL35dBE-woa_m1_PpgdxA_8BzWPtIg |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Fixed-outline+floorplanning%3A+enabling+hierarchical+design&rft.jtitle=IEEE+transactions+on+very+large+scale+integration+%28VLSI%29+systems&rft.au=Adya%2C+S+N&rft.au=Markov%2C+IL&rft.date=2003-12-01&rft.issn=1063-8210&rft.volume=11&rft.issue=6&rft_id=info:doi/10.1109%2FTVLSI.2003.817546&rft.externalDBID=NO_FULL_TEXT |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1063-8210&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1063-8210&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1063-8210&client=summon |