APA (7th ed.) Citation

Adya, S., & Markov, I. (2003). Fixed-outline floorplanning: Enabling hierarchical design. IEEE transactions on very large scale integration (VLSI) systems, 11(6), 1120-1135. https://doi.org/10.1109/TVLSI.2003.817546

Chicago Style (17th ed.) Citation

Adya, S.N, and I.L Markov. "Fixed-outline Floorplanning: Enabling Hierarchical Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 6 (2003): 1120-1135. https://doi.org/10.1109/TVLSI.2003.817546.

MLA (9th ed.) Citation

Adya, S.N, and I.L Markov. "Fixed-outline Floorplanning: Enabling Hierarchical Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, 2003, pp. 1120-1135, https://doi.org/10.1109/TVLSI.2003.817546.