Low-cost ANS encoder for lossless data compression in FPGAs

We present the implementation of the hardware ANS compressor in FPGAs. The main goal of the design was to propose a solution suitable to low-cost, low-energy embedded systems. We propose the streaming-rANS algorithm of the ANS family as a target for the implementation. Also, we propose a set of algo...

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Bibliographic Details
Published in:International Journal of Electronics and Telecommunications Vol. 70; no. 1; p. 219
Main Authors: Pastuła, Magdalena, Russek, Paweł, Wiatr, Kazimierz
Format: Journal Article
Language:English
Published: Warsaw Polish Academy of Sciences 01.01.2024
Subjects:
Algorithms
asymmetric numeral systems(ans)
Codec
Data compression
Embedded systems
Energy consumption
fpga
hardware codecs
lossless compression
Lossless equipment
Low cost
Parameters
ISSN:2300-1933, 2081-8491, 2300-1933
Online Access:Get full text
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Summary:We present the implementation of the hardware ANS compressor in FPGAs. The main goal of the design was to propose a solution suitable to low-cost, low-energy embedded systems. We propose the streaming-rANS algorithm of the ANS family as a target for the implementation. Also, we propose a set of algorithm parameters that substantially reduce the use of FPGA resources, and we examine what is the influence of the chosen parameters on compression performance. Further, we compare our design to the lossless codecs found in literature, and to the streaming-rANS codecs with arbitrary parameters.
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content type line 14
ISSN:2300-1933
2081-8491
2300-1933
DOI:10.24425/ijet.2024.149534