Integrated Memory Controllers with Parallel Coherence Streams

Previous work in scalable hardware distributed shared memory (DSM) multiprocessors has established the critical and dominant role that protocol processing bandwidth (or its inverse, occupancy) plays in determining overall performance in architectures with standalone memory/coherence controllers. How...

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Veröffentlicht in:	IEEE transactions on parallel and distributed systems Jg. 18; H. 8; S. 1159 - 1173
Hauptverfasser:	Chaudhuri, M., Heinrich, M.
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.08.2007 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Analytical models Bandwidth Coherence Control systems Controllers Distributed memory Engines Hardware Memory architecture Microorganisms Microprocessors Performance enhancement Protocol Protocols Streams Studies System-on-a-chip
ISSN:	1045-9219, 1558-2183
Online-Zugang:	Volltext
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