Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive ca...

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Bibliographic Details
Published in:IEEE transactions on parallel and distributed systems Vol. 29; no. 5; pp. 1174 - 1187
Main Authors: Caheny, Paul, Alvarez, Lluc, Derradji, Said, Valero, Mateo, Moreto, Miquel, Casas, Marc
Format: Journal Article Publication
Language:English
Published: New York IEEE 01.05.2018
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Arquitectura de computadors
Cache coherence
Coherence
Computer architecture
Gestió de memòria (Informàtica)
Hardware
Informàtica
Memory management (Computer science)
NUMA
Parallel processing (Electronic computers)
Processament en paral·lel (Ordinadors)
Protocols
Resource management
Run time (computers)
Runtime
Scheduling
Sockets
Switched mode power supplies
Task-based programming models
Traffic speed
Àrees temàtiques de la UPC
ISSN:1045-9219, 1558-2183
Online Access:Get full text
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Summary:Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves programmability. However, ccNUMA architectures require sophisticated and expensive cache coherence protocols to enforce correctness during parallel executions, which trigger a significant amount of on- and off-chip traffic in the system. This paper analyses how coherence traffic may be best constrained in a large, real ccNUMA platform comprising 288 cores through the use of a joint hardware/software approach. For several benchmarks, we study coherence traffic in detail under the influence of an added hierarchical cache layer in the directory protocol combined with runtime managed NUMA-aware scheduling and data allocation techniques to make most efficient use of the added hardware. The effectiveness of this joint approach is demonstrated by speedups of 3.14× to 9.97× and coherence traffic reductions of up to 99 percent in comparison to NUMA-oblivious scheduling and data allocation.
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ISSN:1045-9219
1558-2183
DOI:10.1109/TPDS.2017.2787123