Optimal design of a VLSI processor with spatially and temporally parallel structure - Kameyama, Michitaka; Sasaki, Masayuki (Electronics & communications in Japan. Part 3, Fundamental electronic science, 1997)
In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to changes of the environment very quickly. Therefore, the development of special‐purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high‐level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 3, 80(8): 1–10, 1997