APA (7th ed.) Citation

Kameyama, M., & Sasaki, M. (1997). Optimal design of a VLSI processor with spatially and temporally parallel structure. Electronics & communications in Japan. Part 3, Fundamental electronic science, 80(8), 1-10. https://doi.org/10.1002/(SICI)1520-6440(199708)80:8<1::AID-ECJC1>3.0.CO;2-O

Chicago Style (17th ed.) Citation

Kameyama, Michitaka, and Masayuki Sasaki. "Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure." Electronics & Communications in Japan. Part 3, Fundamental Electronic Science 80, no. 8 (1997): 1-10. https://doi.org/10.1002/(SICI)1520-6440(199708)80:8<1::AID-ECJC1>3.0.CO;2-O.

MLA (9th ed.) Citation

Kameyama, Michitaka, and Masayuki Sasaki. "Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure." Electronics & Communications in Japan. Part 3, Fundamental Electronic Science, vol. 80, no. 8, 1997, pp. 1-10, https://doi.org/10.1002/(SICI)1520-6440(199708)80:8<1::AID-ECJC1>3.0.CO;2-O.